Collaborative tools bring chip, package
and PCB designer together to improve the system design process.
As I/O counts and power/ground connections continue to increase, the density and pitch of BGA ball patterns are making it increasingly difficult for PCB designers to develop efficient escape strategies. The problem is magnified when traditional chip-driven I/O planning does not consider PCB routing or components when mapping I/Os to BGA balls. The result is increasing cost due to additional layer counts, added complexity and longer design times.
The answer to this problem may be found with a new methodology called PCB-driven I/O planning and placement, where PCB escape routing and component placement are considered upfront in the planning process. Developing a PCB-friendly I/O plan could have significant impact in keeping layer counts and complexity down to control PCB costs.
This methodology is so new and innovative that questions arise over how it can be implemented and the effect it can have on PCB cost. In fact, several of the same value propositions used for packaging can be applied to PCB design, beginning with cost savings. Reducing the layer count on the PCB by pre-escape routing large BGAs will optimize layer usage, for example. By pre-defining the routing, final design time can also be saved because the most difficult challenges are already done.
Moving on to performance improvements, PCB designers also do pre-routing analysis to determine the best routing strategy to use for each design. PCB routing, with tens of thousands of connections, is complex and can take an inordinate amount of time. Pre-planning includes pre-placement of packages on the PCB that will eventually need to communicate with each other. This phase is when PCB designers want to pre-define the I/O plan on packages to meet routing and performance targets. It’s also where a PCB-driven I/O planning and placement methodology can be especially useful. PCB designers currently pre-define package ball-outs and hand the mapping over to the package designer, who also get I/O placement from chip designers. Their unenviable task is to unravel the inevitable spaghetti they are handed. This new methodology can help here as well because it can drive the I/O plan from package balls, as defined by the PCB designers, into the chip.
The methodology has already offered a welcome change to design teams because, as noted above, there has been no tool able to manage a PCB-driven flow into the chip space. The ideal scenario from a PCB designer’s perspective would look something like this: Early in the design phase, the designer would do pre-placement planning of all components on the PCB to optimize the design. This pre-planning would determine which quadrants to use for a specific group of nets so that they result in the shortest length of PCB routing.
The pre-planning strategy then gets passed over to software capable of performing route planning on the package using the PCB guidance. Results drive the I/O planning on the chip, establishing where blocks of I/Os should be placed to best fit the PCB plan. Because this is the planning phase, only the initial data is needed and not specific I/O and nets. This enables chip designers to begin their floorplanning on the chip using the proposed I/O plan defined earlier, a key consideration for optimizing the three domains – chip, package and PCB.
All three design groups are now working from the same proposed I/O plan, with PCB designers taking this initial pre-placement plan to begin routing studies used to fine tune the I/O plan on the PCB. Inevitably, there will be changes to the proposed plan, and PCB-driven I/O planning and placement software could be used to arbitrate conflicts. Of course, chip designers will want changes. Again, this new software will be the mechanism for making those changes.
Let’s suppose the chip designers determine that they need to move a block in the core because they cannot get timing to converge. The move means the associate I/O also needs to move, which changes the package and PCB. Can the changes be made in the package without affecting the ball assignments that would affect the PCB? The answer could be “yes” because the software determines that changes can be managed in the package without changing the PCB, closing the arbitration. However, the answer could be “no” if changes cannot be made without changing the I/O on the package balls and adding more layers to the package, which is costly.
One solution is to push changes down to the PCB designers to see if they can manage them, using the software for arbitrating a compromise. If the proposed I/O changes cannot be managed at the PCB or package level without adding significant cost, then the issue gets pushed back to the chip designers to arbitrate a reasonable solution.
While all this sounds intriguing, what about the previous methodology? It was great in theory but hard to implement, especially when it needed to capture design intent from the three domains to be able to perform tradeoffs with all the constraints to arrive at a sensible solution.
This new methodology includes synthesis, placement and routing, supported by the ability to analyze timing, power and signal integrity. At the heart of a PCB-driven I/O, planning and placement methodology is a unified data model represented as a common database to capture chip, package and PCB design intent. A unified data model would give designers the ability to explore tradeoffs on the chip and package with immediate feedback, including a complete understanding of chip, package and PCB constraints with both electrical and physical attributes. It would help resolve I/O-related questions that come up throughout the design cycle, giving immediate pointers on effects from any I/O change to the chip, package or PCB floorplan.
A graphical user interface would be used to collect and manage I/O data in an integrated bump BGA map, instead of the well-used but error-prone general-purpose spreadsheet. Instead, the unified data model would serve as a dynamic repository with the correct state of the I/O plan, supporting industry-standard data files to function within existing flows.
Because signal and power integrity are becoming more and more critical to the success of system-level I/O planning, the methodology should have the ability to evaluate the electrical performance as part of the planning process flow. I/O planning and placement needs a variety of analysis engines as well. Since the methodology is a planning environment where all data may not be present and the design is incomplete, extraction and analysis software must be flexible enough to account for these limitations.
Extraction/estimation is used to obtain initial parasitics information about the system interconnect. While final signoff accuracy requires use of a full 3D field solver and simulation tools from companies such as Sigrity and Optimal Corp., early-stage analysis benefits from fast estimates of parasitics. In these early stages, PCB traces can be represented as distributed resistance, inductance and capacitance (RLC) circuits with standard terminations such as series resistors. Moving forward, package-level routing and voltage domain plane cutting need to be design rule check (DRC) clean. They must abide by packaging rules to establish valid chip-to-package net assignments and proper power plane bump/ball assignments.
The planning of the I/O rings begins with synthesis and placement, where a correct-by-design I/O ring is created to satisfy a set of constraints, including board-level I/O requirements, signal/power/ground (SPG) requirements, rules-based I/O sequencing, package design rules and the initial core floorplan of the chip. Signal and power-integrity factors must be considered, including power and ground needs of I/O drivers, and load conditions to meet these requirements. Synthesis must calculate current requirements of a voltage plane based on driver models, and then calculate the number of balls needed to meet those requirements. For designs with multiple voltage domains, synthesis must accommodate the needs of each power domain.
In addition to supporting PCB or system-level requirements, the synthesis engine needs to optimize the I/O ring plan to minimize die size, core and I/O row area. If the die size is fixed, the synthesis algorithm can succeed only if a feasible I/O ring plan exists for the given die size. Whenever possible, the optimized plan should maximize the usable area for core placement. The placement engine must place I/Os, bumps or bond pads, and assign nets to pins/balls. Before synthesis, it should estimate I/O cell placement around the periphery of the die. This placement must accommodate requirements such as pre-placed instances, hard macros and groupings of I/O cells along with electrical constraints.
A PCB-driven I/O planning and placement methodology can generate sequenced I/O placement once the I/O ring has been synthesized. RLC information can be extracted for the nets and analyzed for I/O timing and noise once the initial route planning has been completed. Delay engines will calculate timing effects due to RLC, conductance and crosstalk, and must be able to calculate the delay associated with individual nets or groups of nets. Delay engines should determine the timing skew for differential pairs, clock switches and data/clock nets, as well.
A signal integrity engine that supplies crosstalk data needed for delay analysis and noise estimation will help optimize the I/O plan in synthesis through the use of extracted package parasitics and IBIS driver models along with estimated PCB load conditions. For power nets, a power integrity engine analyzes voltage and current values and frequency-domain analysis will determine de-coupling strategies. Time-domain analysis reviews electrical characteristics and groups of signals based on RLC and mutual coupling. This type of integrity analysis can enable I/O planning software to optimize power/ground-to-signal ratios. Additionally, I/O planning can collect various I/O data in use and provide a path from chip to PCB designers.
It is difficult for one person to explore all of the possible tradeoffs and the impact of each quickly enough to uncover an optimized solution across these three domains. Each design group can look at their area, make some proposed changes and pass them along, not knowing the impact on the other groups’ work, a time-consuming and impractical chore when changes are coming daily.
Silicon design teams must bring PCB-aware I/O planning into the silicon design flow to close the gap between silicon core functionality and the packaging and PCB requirements. Previously, they have ignored PCB requirements and endured longer time to market, higher costs and compromised performance. With PCB-aware I/O planning, they can reduce costs through die size reduction, the use of less expensive package technology and reduced PCB complexity. With this methodology, the system design cycle will be shorter due to concurrent chip, package and PCB design flows that simplify I/O management, helping beat time-to-market pressures. Chips will offer higher performance due to realistic design constraints and the ability to manage power, signal integrity and timing to the PCB.
More importantly, PCB-aware I/O planning enables design groups to get early information about the impact of the initial I/O plan on the package and PCB needed for a specific design, which also helps manage cost and schedule projections.
A chief concept is that PCB-driven I/O planning must be part of the overall system design flow, allowing chip, package and PCB designers to deal with issues early in a collaborative design flow.
Each of these three design domains requires unique skill sets that are developed over years. As such, the design flow must enable experts from each domain to contribute their knowledge and experience to the final plan. Chip designers cannot be expected to understand all the requirements of the package and PCB design. The right solution is to develop a methodology that includes design tools that enable this collaborative environment. With this methodology, each group can offer guidance to help meet their overall product goals and market requirements. PCD&M
Joel McGrath is director of technical marketing at Rio Design Automation Inc. He can be reached at This email address is being protected from spambots. You need JavaScript enabled to view it..
