AUSTIN – Flip chip in package is expanding in mobile computing, especially smartphones and tablets. In units, the compound annual growth rate from 2011 to 2016 is almost 26%, says TechSearch International.

In number of wafers, the CAGR is 13.5% because much of the growth is for small-size die, says the research firm.

The industry is experiencing a transition from solder bump to copper pillar, just as it moved from an evaporated bump to a plated process, the firm’s recent report says. While the transition to copper pillar is underway, SnAg remains the Pb-free solution of choice. Using current exemptions, some companies continue to ship products with eutectic and high-Pb solder bumps.

Increased demand for thinner, lighter-weight portable products continues to drive wafer level package growth. The CAGR for WLPs in units from 2011 to 2017 is almost 13%, while the CAGR in wafers is slightly over 14%, according to TechSearch.

While many wire bond designs are transitioning to WLP, some FCIP is also converting to WLP. Analog devices account for large shipment numbers in both units and wafers, but shipments of devices with RF functions are also contributing to strong growth. WLPs have historically been used for low-pin-count applications (≤100 I/O).  However, many companies plan to use WLPs for higher-pin-count applications with larger die sizes, up to almost 8mm on a side, says the firm.

In the case of larger die sizes, companies will have to trade off conventional fan-in technology with 0.35mm or finer ball pitch versus moving to fan-out solutions.

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