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  • How the PCB Stackup Helps Control EMI

    How the PCB Stackup Helps Control EMI

    Power and signal placed on outer layers minimize radiated emissions.
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  • Century Circuits

    Century Circuits

    Which PCB technologies are best suited to survive 100 years?
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  • Learning from the Past

    Learning from the Past

    What history can tell us about our position in high-tech.
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  • Thermal Vias are Ineffective. Here’s Why.

    Thermal Vias are Ineffective. Here’s Why.

    Adding thermal vias can take up valuable board space with little benefit.
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  • Connecting the Industry, from Boards to Assemblies

    Connecting the Industry, from Boards to Assemblies

    HDP is embarking on new rounds of evaluations of laminates and lead-free solders.
      READ MORE...

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Design News

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Category: Design News
WILSONVILLE, OR– Mentor Graphics reported second-quarter revenue of $182.4 million, with a GAAP loss of $.19 per share, and a non-GAAP loss of $.02 per share.

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Category: Design News
NAPA, CA—Accellera announced that its Board of Directors and Technical Committee members approved a new version of the Verilog-Analog Mixed-Signal (AMS) standard, Verilog-AMS 2.3. The new Verilog-AMS standard unifies the Verilog-AMS 2.2 specification with the IEEE Std. 1364 and the Verilog hardware description language (HDL) standard.

Verilog-AMS 2.3 allows EDA software tool developers to implement EDA tools without ambiguities in the language interpretation. This version encompasses analog and mixed-signal extensions to IEEE Std. 1364 used in digital circuit design and verification.  

The AMS standard is a result of the efforts of the Technical Committee members. To participate in the Accellera AMS Technical Committee efforts, please visit www.accellera.org/activities/verilog-ams/.

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Category: Design News
YAVNE, ISRAEL- Despite the slump in the global economy and the weak U.S. dollar, Valor Computerized Systems Ltd. experienced an increase in profits for 2008.

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Category: Design News
SANTA CLARA, CA -- Agilent Technologies Inc. has released an integrated design flow solution that includes full 3D EM simulation for RF module design. According to the company, EMDS-for-ADS can help the designer accurately predict the 3D EM interactions of embedded passive components in RF modules.

“The 3D EM simulator allows our RF module designers to replace standalone tools such as HFSS,” said Bob Wong, R&D engineer with Agilent’s Component Test (Network Analyzer) Division. “As a result, we’ve more than doubled our design efficiency because we can interactively co-simulate the circuit and physical 3D effects without leaving the ADS design flow.” 
 
The most common applications for EMDS-for-ADS are RF modules based on LTCC (low temperature co-fired ceramics) and laminates with embedded passive structures. EMDS-for-ADS uses planar RF layout macros to automatically draw RF components such as spiral inductors and meander lines, reducing design time.

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Category: Design News
SAN JOSE, CA -- Cadence Design Systems, Inc. releases new Allegro PCB tools for HDI designs that includes new objects, an extensive set of new rules for microvias, an enhanced via-transition use model, and changes to the entire PCB design flow to enable a comprehensive constraint-driven HDI design flow.

Design partitioning has been enhanced with new capabilities for partitioning the design horizontally and adding soft boundaries to allow users to work in parallel more efficiently, further shortening the design cycle.

These HDI design upgrades are part of the Cadence SPB 16.2 that also addresses chip package design challenges. According to the company, the SPB 16.2 release improves (SiP) miniaturization, design cycle reduction and DFM-driven design. It incorporates a new power integrity modeling solution. These new capabilities can boost productivity of digital, analog, RF and mixed-signal IC package designers involved in single and multi-die packages/SiPs.

Design teams can expect improvements in the reduction in overall package size through the introduction of rules and constraint-driven automation capabilities that address the design methodology of high-density interconnect (HDI) substrate manufacturing that is a key enabler for miniaturization and increased functional density. Overall design time can be reduced through the enablement of team-based design, where multiple designers can work concurrently on the same design in order to reduce design cycle times and speed time to market.  
 
SPB 16.2 will be demonstrated at the EMA booth at the PCB West in Santa Clara, CA, Sept 14-19.

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Category: Design News
SANTA CLARA, CA -- Sigrity Inc. and The Research Foundation of State University of New York (SUNY) have filed a lawsuit against Ansoft Corp. and ANSYS, Inc. for infringement of U.S. Patent No. 5,504,423 titled "Method for Modeling Interactions in Multilayered Electronic Packaging Structures.”

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