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Zuken Offers DDR3 Timing Webinar

Published: 21 April 2014
 by Chelsey Drysdale

WESTFORD, MA – On Apr. 23, Zuken is offering a webinar on how to realize a DDR3 system using constraints and validate the design’s timing margins.

Starting with schematics, Zuken creates what-if scenarios, enters constraints, and reviews initial eye diagrams. Next, the firm uses the constraints to guide placement and routing. Finally, with constraints met, they perform signal integrity analysis and verify that setup/hold margins are honored. Webinar attendees will learn to identify length matching rules in a JEDEC DDR3 specification; implement rules as constraints for the DDR3 signals; perform placement and routing per the constraints; run signal integrity analysis, and verify setup and hold margins. To register, visit http://pages.zuken.com/Webinar4-Registration.html.

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