SAN JOSE, CA – Cadence Design Systems was selected by the Defense Advanced Research Projects Agency (DARPA) to support the Intelligent Design of Electronic Assets (IDEA) program.
This is one of six new programs within DARPA’s Electronics Resurgence Initiative (ERI) to use advanced machine learning techniques to develop a unified platform for a fully integrated, intelligent design flow for SoCs, SiPs and PCBs.
“This program will accelerate our roadmap toward realizing intelligent design flows for the next big leap in design productivity,” said Dr. Anirudh Devgan, president of Cadence. “This program will set the stage for enhancing the entire span of our analog, digital, verification, package and PCB EDA technologies, providing our customers with the most advanced system design enablement solutions.”
To fulfill the program charter over the four-year term of the contract, Cadence created the Machine learning-driven Automatic Generation of Electronic Systems through Intelligent Collaboration (MAGESTIC) research and development program. This program will create a foundation for system design enablement by introducing greater autonomy within the design process and developing design-intent-driven products.
The Cadence-led team includes Carnegie Mellon University and NVIDIA.
The MAGESTIC program aims to address advancing the state of the art in machine learning to develop algorithms that optimize performance; extending support for advanced CMOS process nodes, including 7nm and below, as well as larger process nodes; automating the routing and tuning of devices to improve reliability, circuit performance, and resilience; demonstrating improved power, performance and area (PPA) utilizing machine learning, analytics, and optimization; staging the introductions of the technology, allowing the system to learn from the users and allowing users to gain an understanding of how to best leverage the tools to achieve desired results.
The program also will extend Cadence’s work in employing cloud-based design systems to handle large-scale distributed processing to speed design efforts.
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