In the evolution of silicon implementation, creative solutions to costly problems have become standard practice. One of these solutions is the use of a “chiplet.” A chiplet is precisely what it sounds like: a smaller version of a chip. This doesn’t mean it’s a miniature version. It means that only critical functions that derive significant benefits from a 5 or 7nm fabrication process are included on the chip. Other functions that will work well with 10nm or greater can then be fabricated with appropriate cost savings.
Chiplet technology creates a challenge, however. If all functions were included in the chip, the interfaces could more easily be measured and evaluated. These items now must be accounted for on a package or, more accurately, a system-in-package (SiP) (FIGURE 1). This places greater importance on the electrical characteristics of those interfaces and how that SiP implementation affects that behavior. Thus, there is a need to rapidly assess these issues with minimal effort for maximum results via virtual prototyping.
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Just about all electronic equipment uses printed circuit boards or flexible circuits for wiring and packaging materials. Electronic companies design their products then place orders for PCBs. Supply chains order accordingly and business trends begin to unfold from the PCB industry. This sounds simple enough, but countries and regions collect manufacturing data differently, so you have to understand statistical industry data before making forecasts.
That’s one of the questions the new leadership at HDP plans to address in 2021.
This month Marshall Andrews stepped down as the longest-serving head of The High-Density Packaging (HDP) User Group. But as Larry Marcanti assumes the role of executive director of the decades-old electronics consortium, don’t expect big changes.
On Andrews’ 15-year watch, HDP’s membership increased by more than 30 companies, to reach more than 50 total. The ongoing project portfolio rose from five to an average of 25 member-driven activities.
Despite the Covid-19 lockdown, HDP is coming off one of its most successful years yet, having completed 13 projects. Marcanti and HDP facilitator John Davignon gave an update of the consortium’s latest work and future plans in an exclusive interview with PCD&F/CIRCUITS ASSEMBLY in December.
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A collaborative educational group formed in January and adapted virtually to bring the industry together.
A year ago, after IPC dissolved the Designers Council, its board members formed the Printed Circuit Engineering Association (PCEA) to continue their pursuit to collaborate, inspire, and educate the PCB design and engineering community.
The PCEA’s mission is to promote the printed circuit engineering profession by encouraging and facilitating the exchange of information and the integration of new design concepts through communications, seminars, and workshops. Its efforts are buttressed by a network of regional chapters and the support of sponsors, including several CAD companies and other firms.
The PCEA has a growing membership of more than 1,000 members, with existing chapters in Phoenix, Orange County (CA), San Diego, Silicon Valley, Ontario (Canada), Minneapolis-St. Paul, Monterrey (Mexico), Nogales (Mexico), Research Triangle Park, and Seattle. Chapters planned for the near future include Columbus-Cincinnati-Dayton; Grand Rapids, MI; Illinois-Wisconsin; New Hampshire-Massachusetts; Albuquerque; Houston; Dallas; and Austin. The PCEA hopes to open another Canadian chapter soon.
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Processes and tools for accurate lab analysis and defect detection.
Electronic sample preparation is a complex process that goes beyond merely lopping a piece off a PCB for inspection. This process involves several, exacting preparation stages.
The process designs each step to specifically adapt to the inspected device’s design, materials, and fabrication technology. Performing any of the preparation stages incorrectly can result in spurious features, artifacts and great potential for both Type I and Type II error.
The process starts with PCB manufacturers designing test coupon segments into each of their products. This function enables panel testing without wasting the actual production board. To confirm the lab has met product specifications, they separate the coupon from each panel.
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