Understanding cap differences and modeling will help identify loop inductance issues early.

We’ve written for months about how to control power delivery. While we have learned the effects of layout on the PDN, we haven’t yet focused on the other major influencing factor: the decoupling capacitor.

These simple, 2-pin devices perform two main tasks: resist a change in voltage across their pins and accumulate and store “charge” that can be delivered from those pins to maintain that voltage. In the world of digital design, this “decoupling” function is huge and is arguably why we do power integrity (PI) simulation in the first place. The power demands of a product’s components are largely defined by its features and performance requirements, which determine supply sizes. Between those lies the power delivery network (PDN), a subject we’ve intensely studied. Composed almost entirely from capacitors and the copper that connects it all together, the success or failure of a PDN is often determined in layout. In previous articles, we’ve written about “loop inductance” and how it impacts the capacitors’ ability to do their job. A solid understanding of cap differences and modeling will help identify loop inductance issues early to ensure a successful PDN.

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