Stackup analysis can help to optimize layer count, trace width and spacing and electrical performance.

Part 1 appeared in the October issue. Part 2 appeared in the December issue. Part 3 appeared in the February issue. All four parts are presented here.

The term “stack-up” refers to the arrangement and the types of layers in a multilayer board. The design of a PCB stack-up involves ascertaining the number of signal layers¹ needed to route the board and the ground/power planes demanded for adequate power distribution. It is recommended that the layers are arranged so that each high-speed trace is referenced to a continuous plane². Furthermore, it is desirable for the stack-up to include parallel (adjacent) power and ground layers for enhancing capacitive decoupling and reducing EMI, and the PCB stack-up will strongly influence impedance of a power distribution system (PDS).

Prepreg (also called B-stage) consists of a glass cloth coated with resin (epoxy) that has not been fully cured. A prepreg layer is applied between two internal layers (or cores) of a multilayer PCB to function as glue through the lamination process. A core is a thin piece of dielectric (cured fiberglass-epoxy resin) with copper foil bonded on both sides. The term laminate also refers to a composition of two sheets of copper foil laminated to a piece of woven glass cloth saturated with resin and fully cured.

The thickness of the copper foil is expressed in ounces³ that represent the weight of copper per square foot of surface area. Three common thicknesses are 0.5 ounce, 1.0 ounce and 2.0 ounce. Copper foil of 1.0 ounce (~1.4 mils) thickness is produced by plating to a thickness sufficient to equal one ounce of copper distributed over a one-square-foot area.

Use of 1.0 ounce copper foil is quite popular in PCB fabrication; however, 0.5 ounce ground/power planes can be sufficient for all high-speed PCBs with exception of those that demand very high power levels. Copper foil that is categorized as 1.0 ounce foil has a thickness of approximately 1.2 mils and 0.5 ounce foil has a thickness of 0.6 mils in the completed circuit board because of of anticipated copper losses that result from the chemical processes used in the manufacturing process. The thickness of plane ground and power layers adds to the total PCB thickness.

Standard PCB thickness values⁴ include 39 mils, 62 mils, 93 mils and 125 mils, but other board thicknesses (for instance 100 mils) can be also obtained. Stack-up parameters such as spacing between layers, substrate dielectric materials and trace dimensions need to be selected properly in order to meet the board impedance and crosstalk requirements.

Several stack-up features can be illustrated by considering a four-layer PCB, as depicted by Figure 1.

Ground and power planes perform multiple functions, one of which is to distribute power to various devices, but they also furnish a means for achieving controlled impedance transmission lines. The plane layers can appreciably diminish noise and radiation levels. At frequencies⁵ exceeding 10 MHz or 15 MHz, incorporation of power and ground layers, such as a multilayer stack-up as opposed to a two-layer board is recommended.

In Figure 1, the layer order from top to bottom is Sig, Gnd, Pwr and Sig, which implies that the outer layers are formed by the signal layers, and the inner layers are the ground and power. Another possibility is to have ground and power plane layers as outer layers (Gnd, Sig, Sig, Pwr). This scheme can provide greater shielding⁶, but it is accompanied by several drawbacks. For example, the planes need to be cut to allow component placement, and rework on the board becomes more difficult.

The stack-up depicted by Figure 1 is a common arrangement for a four-layer PCB; the parallel power and ground planes can furnish interplane capacitance³ which is important in the stack-up design of high-speed PCBs.

The capacitance produced by a parallel plate capacitor is directly proportional to the area of plates and inversely proportional to their separation⁷. In Figure 2, Mathcad is applied to compute and to plot interplane capacitance (per unit area) for two different dielectric materials. These include Isola 370HR (in red) and Rogers 4320 (in blue). The Isola 370HR material is a high performance 180ºC glass transition temperature (Tg) system for PCB applications where maximum thermal performance and reliability are entailed.

Rogers 4320 (prepreg) and 4350 (laminate) are glass-reinforced⁸ ceramic thermosets that are available in several thicknesses with dielectric constant εr = 3.5 and loss tangent Tan(δ) = 0.004. In general, Rogers RO4000 series⁹ are low-loss materials that can be economically fabricated via standard epoxy/glass processes. They are designed with excellent high frequency performance and low cost circuit production in mind.

The capacitance resulting from two adjacent plane layers plays a crucial role in the power delivery system (PDS) of high-speed boards. Since such parallel plate capacitance is inversely related to the separation of the plane pairs, it is desirable to keep the planes near each other. However, there are two important limitations³ concerning how close the planes can be fabricated. These restrictions relate to the capability of PCB manufacturer to laminate the planes without causing shorts and to preserve minimum dielectric thickness to meet insulation standards.

Normally, PCBs cannot provide adequate interplane capacitance⁵ to successfully meet decoupling requirements below 500 MHz. When this occurs, other decoupling methods, such as employment of discrete capacitors, are then needed.

Let us consider the six-layer structure of Figure 3, which includes both outer (microstrip) and inner (stripline) traces. For a surface microstrip¹⁰ the signal conductor is exposed to air, so the effective dielectric constant will be somewhere between that of air (which equals 1) and the dielectric constant of the substrate below the trace. The signal speed is influenced by the effective dielectric constant with the surface microstrip usually offering the fastest propagation velocity¹⁰.

After plating, outer-layer traces have greater trace-width variation than innerlayer traces. This implies that stripline traces provide superior impedance control as compared to microstrip lines. However, striplines can cause stubs¹¹ when through-hole vias are used, as illustrated by Figure 3.

The configurations depicted by Figures 3a and 3b (which involve connection to stripline traces) result in stubs due to unused via portions (the segments which extend past the vias’ last connecting layer). However, the case of Figure 3c, in which two microstrip transmission lines are connected, can shun via stub formation.

Bogatin¹² presents an interesting comparison of microstrip vs. stripline traces in terms of impedance control, differential pair coupling, attenuation, far-end crosstalk and routing density. Generally, higher-density PCBs are less expensive, but closely spaced traces can result in crosstalk issues. The PCB manufacturing cost is directly related to the size of the PCB and the number of layers¹³.

When designing a PCB stackup, it is essential to consider crosstalk¹ requirements. Depicted by FIGURE 4 are two single-ended traces having line width W, thickness t, edge-to-edge separation Sn and height over reference plane H. Er is the relative dielectric constant of the substrate.

In order to minimize crosstalk, it is desirable to set H as small and Sn as large as allowed by board target impedance and routing restrictions.¹⁴ The effect of these stackup parameters on crosstalk¹⁵ is disclosed by Equation 1 (FIGURE 5).

Lm is mutual inductance between two neighboring wires, H equals the thickness of the dielectric substrate and L is the line inductance. The center-to-center spacing (s) and edge-to-edge spacing (S_n) for two traces of width W are directly related as shown by Equation 2 (Figure 5).

Crosstalk requirements control trace separation (pitch), which in turn influences board density and the number of routing layers. From Equations 1 and 2, it follows that crosstalk noise (between two neighboring traces) being proportional to mutual inductance, decreases as Sn increases or H decreases. Optimizing trace separation is also valuable for controlling crosstalk between two coupled differential pairs, as illustrated in FIGURE 6.

Crosstalk between differential pairs 1 and 2 can be diminished by widening Sn. A study of far-end crosstalk (FEXT) and crosstalk-induced jitter involving two edge-coupled differential pairs of W = 5 mil and interapair separation Sp = 5 mil, revealed that increasing the pair-to-pair spacing Sn from 5 mils to 20 mils can significantly reduce FEXT¹⁶ and deterministic jitter (DJ). Other measures to avoid crosstalk problems include minimizing parallel run lengths, incorporating guard traces¹⁵ and orthogonally routing the signal lines which belong to adjacent routing layers.

To attain good signal integrity, a clean¹⁵ unobstructed return path is demanded for high-speed signals. Signal and power quality degradation can occur in PCBs and IC packages due to high-speed traces traversing¹⁷ plane-splits.

Plane layers fulfill several duties in power distribution networks (PDNs). They can transfer DC current from source to load, connect bypass capacitors to active components and furnish a return path¹⁸ for the signals. Current flows on power distribution in a manner to diminish total impedance.¹⁹ At low frequencies, this translates to minimizing resistance by spreading²⁰ over every possible path. At high frequencies, the return current crowds under the signal (on reference plane) to minimize inductance.

It is important to avoid splits on ground or power planes, but there are situations when it is inevitable.²⁰ For instance, power islands and moats arise when multiple powers are incorporated on the same plane. Sometimes, it is necessary to allow a plane layer cut-out beneath a connector²¹ in order to lessen the mounting pad capacitance.

Under such circumstances, when cutouts on reference planes are unavoidable, it is critical not to route high-speed buses over such voids (unless the plane with slots is sandwiched between two uniform/continuous planes).

The return current path is also interrupted whenever a signal transitions from one layer to another and changes reference planes. It is then desirable to place near the signal via²² another via (if both reference planes are of same type) or a decoupling capacitor (if one reference plane is a ground while the other one is power). This can furnish for the return current a high-frequency lane between the two reference planes.

Thickness of metal (i.e. plane and signal) layers is a significant option when constructing PCB stackup. Thicker cladding offers lower resistance and symbolizes a good selection for power planes¹⁹. Thinner cladding sustains narrow lines with superior width control; hence, thin cladding is often a logical preference for signal layers to achieve high density routing.

Utilizing 0.5 oz copper for signal layers is a good choice for impedance control³ since only a very small amount of etching is necessary to produce a trace. This allows controlling the trace width to within +/- 0.5 mils. However, there are also cases in which thicker traces are desired in order to decrease the trace’s DC resistance (or for realizing superior thermal performance), although it is more difficult to attain impedance control for thicker traces.

Accomplishing impedance control for high-speed, single-ended signals (such as memory buses and CPU interfaces) and differential pairs (high-speed serial-links, differential clocks, etc.) is vital in stackup design.

Mathematical equations exist for calculating single-ended and differential impedance²³. These formulas offer useful insight regarding how impedance depends on various stackup parameters (e.g., dielectric constant, trace width, dielectric thickness). For instance, Equation 3 (Figure 5) which is an IPC recommended²³ approximation for microstrip impedance, reveals that Zo decreases as the dielectric constant (Er) increases, copper thickness (t) increases or trace width (W) increases. Furthermore, Zo increases as dielectric height H increases. Equation 4 (Figure 5), which applies to edge-coupled microstrip using FR4 material²³, illustrates that differential impedance Zdiff is a function of Zo (the uncoupled single-ended characteristic impedance for each trace), edge-to-edge separation between traces Sn and dielectric thickness H.

Impedance formulas can provide helpful insight and more precise results than rules of thumb approximations, but the accuracy of such analytical techniques is usually limited to about 10%. Ascertaining impedance to a higher degree of exactness would require the use of a field solver program.

Whenever a PCB undergoes modifications, it is necessary to perform stackup analysis²⁴. Such assessment considers optimum number of layers, board size, routing density, copper weight, power needs, PCB thickness, dielectric materials, trace widths/separation, most favorable impedance, price and manufacturability.

Application of HyperLynx Stackup Editor for impedance planning is illustrated by FIGURE 7. The Stackup Editor allows adding or subtracting layers and incorporating soldermask.

For each dielectric, it permits selecting technology (prepreg or core), thickness, dielectric constant and loss tangent. For metal layers, it allows defining metal type (for correct resistivity and temperature coefficient). Trace widths and thickness can be specified for each signal layer. The Zo Planning tab allows for specifying target impedance (for single-ended or differential pairs) and then solving for various parameters (trace width, separation).

Figure 7 shows a stackup consisting of eight layers. An eight-layer stack⁵ can satisfy several desirable requirements, including multiple ground and power layers. In this case each signal layer is adjacent to a tightly coupled plane layer, and the signal layers are located between planes layers (and are thereby being well shielded).

In order to minimize warping, it is desirable for the stackup to be symmetrical and well balanced²⁵. Normally, an N-layer PCB includes N metal layers separated by N-1 dielectrics, and N should be an even number to avoid warpage¹⁹.

Another measure to accomplish uniformity is to add dummy copper pads (thieving) to open areas on the PCB’s outer layers. This aids in attaining a uniform copper distribution across the whole board surface.

Pouring copper on outer layers and grounding it with multiple vias can enhance shielding, reduce crosstalk and improve heat dissipation.²⁶ Furthermore, copper/ground flooding (not to be confused with thieving, which involves applying dummy copper pads) influences impedance and can convert mictrostrip lines into coplanar configuration. Such geometries can be efficiently analyzed with Polar Instruments’ Si8000 software²⁷ that employs Boundary Element Modeling to forecast the finished impedance of various PCB structures.

FIGURE 8 exemplifies impedance computation for a coplanar differential pair.

The parameters comprise trace width = 12 mil, trace thickness = 2 mil, dielectric thickness = 8 mil, dielectric constant = 3.38, intrapair separation = 15 mil, line to ground clearance (horizontal) = 10 mil, solder mask thickness = 0.8 mil and solder mask dielectric constant = 4.5. Si8000 predicts differential impedance of 100.43 Ω. This denotes a nominal calculation, but frequently it is necessary to consider impedance tolerances.

A typical tolerance value is +/- 10%. A differential impedance of 100 +/- 10% implies variation from 90 Ω to 110 Ω. Sometimes, it is desirable to have a tighter tolerance such as +/- 5%, since impedance tolerance often involves trade-off between impedance of PCB traces, package, driver output impedance and termination resistors. Tightening the PCB trace tolerance makes it feasible to relax the constraints on other parameters (package, driver, termination), but this also increases board fabrication cost. A 5% tolerance is more expensive to manufacture than a 10% tolerance, which is costlier than a 15% tolerance.²⁵

Three main materials³ in a multilayer PCB embrace copper foil sheets, resin and woven glass cloth. Cores or laminate sheets are constructed by affixing copper foil to one or both sides of fully cured prepreg sheets. Prepreg mats are a weave of glass fiber yarns preimpreganted²⁸ with partially cured resin.

Several resin types are utilized for prepreg preparation. These resin systems usually differ in electrical properties (such as dielectric constant and loss tangent) and mechanical/thermal characteristics (coefficient of expansion, glass transition temperature and rate of moisture absorption).

The commonly used FR-4 has a woven glass/epoxy resin composition.

However, there are alternatives such as GETEK, MEGTRON, BT, polyamide²⁸ and cyanate resin material, with attractive mechanical or electrical properties (low dielectric constant and loss tangent).

Fibers are applied to strengthen the resins; these comprise the electrical grade E glass and structural grade S glass. E glass is more common, but S glass is stronger and has lower Er (also more expensive) than E glass. Addition of fiber to resin alters the electrical and mechanical characteristics of the composite structure based on glass-to-resin ratio. FR-6 utilizes a polyester²⁹ resin system plus glass matte reinforcement and is suitable for flame resistant³⁰, low capacitance or high impact applications.

Solder mask / resist is a coating that protects PCB traces and prevents solder bridges and shorts. It facilitates wave soldering applied in mass assembly. Solder mask is a lacquer-like polymer layer often applied with a green tint, but it is available in various colors and finishes. A common solder mask³¹ is Liquid Photo Imagable (LPI).

For a multilayer PCB, the copper thickness does not have to be the same for all stackup layers. It is also unnecessary for all the cores to be of the same laminate. Hybrid-type construction has been gaining popularity. The PCB conductor and dielectric losses³² constitute another critical consideration.

The DC conductor resistance is governed by Equation 5. All of the Equations can be found in FIGURE 9. Here, R_dc represents resistance per unit length for DC currents, ρ is the bulk conductor resistivity³³, W is trace width and t is thickness. The conductor DC losses are directly related to R_dc and are frequency independent.

DC losses are negligible for short traces of large crosssections and become important for long lines of small cross-sectional geometries and for multi-drop topologies. In Equation 6, R_ac symbolizes the AC conductor resistance per unit length and δ is the skin depth. R_ac can be reduced by widening the trace width. It varies inversely with δ and directly with √f. When ascertaining the total AC resistance, it is necessary to also account for resistance of return current on the reference plane. Furthermore, the conductor AC loss is directly related to R_ac and hence proportional with the square root of frequency.

Equation 7 is a skin depth expression with σ being the conductor’s conductivity (inverse of resistivity ρ), μ0 is permeability of free space, μr is conductor’s relative permeability and f is sine-wave frequency. When f is in Hz, σ in Siemens/meter and μ0 in Henries/meter (4∏E-7), then Equation 7 produces ÏŒ in meter. Equation 8 is a simplified skin depth formula³⁴ applicable to copper ( σ = 5.6E7 Siemens/m and μr =1), with fmhz being frequency in MHz and δcu in micron.

In Equation 9 αdiel represents attenuation associated with dielectric loss 32 in dB/in, fghz is frequency in GHz and Er is substrate dielectric constant.

FIGURE 10 presents dielectric loss - αdiel (based on Equation 9) for several materials, generated with the aid of Mathcad. The curve RO4 (Rogers 4350) displays the least and FR-6 the most attenuation in this comparison.

NeS (Nelco N4000-13SI), which utilizes S glass, is less lossy than NeE (Nelco N4000-6 Hi Tg FR4), based on E glass.

At high frequencies, for typical PCB trace dimensions, the dielectric losses being proportional to frequency can become dominant³² over conductor DC losses (frequency independent) and AC losses (proportional to √f ).

In addition to conductor and dielectric losses, the effects due to roughness of conductor surface can be significant. Conductor roughness is often expressed as tooth structure¹⁴ and the amount of surface variations is portrayed as tooth size. Conductor surface roughness can effectively increase the material resistance when the mean surface roughness is a significant percentage of skin depth. For instance, at a frequency of ~ 200 MHz, the skin depth of copper is 4.667 micron, which approximately equals the typical PCB surface roughness ( ~ 4 microns to 7 micron). Frequency harmonics exceeding 200 MHz will then deviate from the ideal loss formulae¹⁴. For producing low loss interconnects, it is desirable to have smooth copper foils.

Conclusion

When selecting PCB materials, some parameters that need to be considered include the conductor and dielectric losses, the electrical characteristics, the mechanical/thermal properties and the price.

There are other important contemplations involved when ascertaining optimum materials for PCB stackup, such as impact of glass weave³⁵ in PCB laminates on Gigabit per second signals and also meeting standards (IPC specifications). These will be discussed in Part 4 of this article.

The dielectric loss plays a crucial role at high frequencies. It relies on the dissipation factor (loss tangent) and permittivity, which are dependent on the dielectric material’s resin system and glass type. For instance, FR-4 (Er = 4.1, tan(θ)=0.022) and Nelco 4000-13 (Er = 3.6, tan(θ)=0.009) both utilize E glass, but the former is more lossy because of a different resin substance. Also, Nelco 4000-13 is more lossy than Nelco 4000-13SI (Er = 3.25, tan(θ)=0.008), since Nelco 4000-13SI is based on S glass while Nelco 4000-13 uses E glass (although they both contain the same resin type).

In addition to dielectric loss, the impact of a dielectric material’s glass weave on high-speed signals deserves attention. The glass weave in PCB laminates³⁶ can cause jitter and skew on Gigabit-per-second (and faster) differential pairs.

FIGURE 11 illustrates an FR-4 based substrate having fiber glass bundles and resin-rich regions.

Er for pure resin epoxy is ~3.8 and for pure (E-glass) fiberglass is ~ 5.8 at 1 MHz³⁷. Due to such inhomogeneous material characteristics, a trace routed over sections of mostly resin³⁸ can experience a different Er than a track running over regions composed mainly of fiberglass bundles. The effective Er of substrate influences the impedance and signal velocity. In some FR-4 constructions, for instance those having 1080 glass, the weave pitch³⁹ in X or Y direction is in the order of 0.016 inches and comparable to a typical signal pitch (0.010 inch to 0.016 inch) for PCB differential pairs. This can cause traces of a coupled differential pair to experience different surroundings and undesirable skew. Differential pairs with long³⁸ horizontal or vertical traces, as depicted by FIGUREs 11A and B, are more susceptible to such skew than tracks that include diagonal sections, as shown by FIGUREs 11c and D. The inhomogeneous dielectric effects are averaged out for diagonally routed pairs.

Numerous solutions⁴⁰ have been proposed to control the fiber weave effect (FWE) in PCBs. These embrace routing signals at a 45-degree angle, implementing an electronic active deskew⁴¹ within the differential pair, using 3313 glass cloth³⁶ (which possesses a more uniform distribution of glass cloth across the surface), applying materials which lack weave³⁹ or utilizing advanced glass fabric⁴⁰.

Another notable task for stackup construction is ascertaining how many signal layers are necessary for routing the board. The number and size of BGAs of the design, fanout patterns⁴², via types and the layout of package balls⁴³ strongly influence the required number of signal layers. Furthermore, the form factor⁴⁴ (which imposes limits on a PCB area) and edge connectors⁴⁵ (which bound the board thickness) also influence the maximum number of layers.

A key objective is to optimize⁴³ the number of layers, while taking performance constraints and cost into consideration.

Whenever six⁴⁶ routing layers are demanded, it can lead to a ten-layer stackup. An example is illustrated by FIGURE 12, which contains four planes and six signal layers.

This was produced by invoking the HyperLynx Stackup Editor, defining/entering the stackup structure and then selecting Edit > Copy Special > Manufacturing Documentation. Figure 12 illustrates the stackup and the key parameters required for PCB construction. This stackup was designed to be suitable for using a dielectric material with nominal Er of 4.0.

A ten-layer board may be constructed in 0.062-inch thickness. The PCB stackup is usually presented as part of a fabrication drawing⁴⁷.

Other important information contained in a fabrication drawing comprises mechanical dimensions, drill charts and notes. The IPC specifications (and class type) should be listed in the notes section. Some examples of related IPC specifications include: IPC-D-356, IPC-4101, IPC6012B and IPC-SM-840C.

IPC-D-356 defines a standard netlist format to represent test information for bare boards, which is supported by test equipment manufacturers. IPC-4101 addresses the requirements for base materials (e.g., laminate or prepreg) applicable mainly to rigid or multilayer PCBs. IPC-6012B covers qualification and performance of rigid PCBs. It relates to final finish and surface plating coating options, conductors, holes/vias, frequency of acceptance and quality conformance, as well as electrical, mechanical and environmental requirements. IPC-SM-840C defines the requisites for qualification and acceptance of permanent solder mask.

When designing a PCB stackup, it is crucial to get the fabricator⁴⁸ involved. The PCB manufacturer can furnish the designer with helpful recommendations and suggestions.

It is also very useful to design and fabricate test coupons⁴⁸ (which are small PCBs with exactly the same stackup as a main board) for TDR⁴⁹ and VNA testing and verifications. Coupon applications will be further described in Part 5 of this column.

Test coupons are small printed circuit boards (PCBs) with exactly the same layers,⁴⁸ trace construction,⁵⁰ plating and solder mask as the main PCB. They are commonly fabricated to achieve certain target impedance values.51

Some impedance coupons contain vias connected to ground and signal planes that are in close proximity at the end of a trace and can serve as probing points. Since test coupons reflect the board stackup, they are well-suited for examining the stackup for accuracy and for ensuring that the PCB meets design objectives such as target impedance and crosstalk requirements. FIGURE 13 exemplifies a coupon having impedance controlled single-ended and differential traces plus thieving (i.e., dummy copper pads).

FIGURE 14 illustrates a section of a high-speed, multilayer PCB designed for time domain reflectometry (TDR)⁴⁹ and vector network analysis (VNA) testing. It comprises three differential pairs having sub-miniature version A (SMA) connectors. These connectors allow easy links to TDR and VNA cables and a clean signal launch, aiding high-bandwidth measurements.⁵² SMAs can also furnish a repeatable and reliable means of signal attachment for compliance testing.⁵³

TDR measurements of a PCB may yield impedance values different from those predicted by impedance equations or field solvers. Such differences can arise due to several reasons including: software inaccuracy, variations of dielectric material’s permittivity, differences between shape of trace cross section modeled for simulation and actual cross sectional shape of manufactured trace, which relates to the etch factor effect.⁵⁴

Frequently, PCB simulations/computations of trace impedance are based on an ideal rectangular cross section;²⁸ whereas, the fabrication process produces traces resembling a trapezoidal cross section.⁵⁵ The trace cross sectional shape influences its inductance, capacitance, resistance and impedance. Subsequently, differences in simulation results (based on rectangular cross sections) and impedance measurements of actual manufactured boards (with a cross section more similar to a trapezoid) can arise. Vertical over or under etching is numerically expressed by the “etch factor”, which equals the ratio of the trace’s thickness (t) to the amount of under/over cut copper (uc), as depicted in FIGURE 15. 

In Figure 15, the trace thickness t was set at 2.0 mil. The data for the graph was generated applying the Ansoft Q3D software, which allows modeling and simulation of both rectangular and trapezoidal trace cross sections.
Thin traces with wide pitch are less likely to be under/over etched than thick traces with small pitch.

Subsequently, it is advantageous to utilize thin (half ounce) copper for a tight pitch-controlled impedance design.
Small etch factor values correspond to overetched lines. They possess smaller capacitance but higher resistance, conductor loss, inductance and impedance than expected (based on a rectangular cross section computation).⁵⁵

When designing a PCB stackup, it can prove beneficial to verify the capabilities⁴⁷ of a PCB manufacturer prior to assigning the board for fabrication. It is important to confirm that the fabrication house can deliver the single-ended (and differential) target impedances for the trace widths, spacing, copper thicknesses, tolerances and dielectric materials specified in the stackup.⁵⁶ If the PCB vendor cannot meet the dimensional requirements of the stackup, some adjustments may be needed in the design parameters.

Furthermore, if the design utilizes high-frequency PCB materials such as Nelco, Rogers or Getek, it is compulsory to verify that the board manufacturer is familiar with such laminates and their fabrication requirements.⁵⁷

Conclusions

The PCB stackup strongly influences the board impedance, signal integrity and EMI performance of the system.
In this five part series, numerous concepts related to stackup creation and analysis have been covered. In Part 1, the four- and six-layer stackups, plus several features of microstrip and striplines, were discussed. Three types of microstrip lines consist of surface (or exposed) microstrip, coated microstrip (usually with solder mask) and embedded microstrip.¹⁰

In Part 2, it was emphasized that target characteristic impedance carries a significant effect on stackup parameters. However, impedance determinations based on rectangular trace cross section can yield values different from the impedance of the actual fabricated board because of etching during the manufacturing process (which results in traces resembling trapezoidal shape).

Part 3 explained that the conductor DC and AC losses and the copper surface roughness have an impact on stackup design. The DC losses are frequency independent and negligible for short traces of large cross sections. However, the DC resistance can become considerable for long or thin traces, especially when they belong to power nets.⁵⁸

In Part 4, it was noted that Fiber Weave Effect (FWE) associated with some glass fabric styles can cause skew⁵⁹ in high-speed coupled differential pairs. Several options to control FWE were also listed.
As explained earlier in this piece, test coupons designed to replicate the board stackup are valuable for ensuring that the PCB will meet design goals such as target impedance and crosstalk requisites.
Finally, in order to harvest superior yields48 of high-speed (impedance controlled) boards, it is vital that the circuit designers, the board engineers and the technical staff of PCB fabricators maintain an effective working relationship and an open communication. PCD&F

ACKNOWLEDGEMENT

I am grateful to Messrs. Nanoo (Frederik) Staal, Mohammad Tabatabai, Afshin Momtaz, Matthew Isaacs and Neven Pischl of Broadcom Corporation, and Ms. Debi Sorensen of Mentor Graphics Corporation.

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34. Abe Riazi, “Maxwell’s Influence on Signal Integrity,” Printed Circuit Design & Fab, December 2007.
35. “PCB Dielectric Material Selection and Fiber Weave Effect on High-speed Channel Routing,” Altera Corporation, AN-528-1.0, May 2008.
36. Lee W. Ritchey, “On The Problem of Jitter and Skew in Gigabit and Faster Signals Caused by Laminate Weaves,” Speeding Edge, February 2007.
37. Howard Johnson and Martin Graham, “High-Speed Signal Propagation Advanced Black Magic,” Prentice Hall, 2003, pgs. 271-273.
38. Abe Riazi, “ Avoiding Differential Pair Routing Violations,” Printed Circuit Design & Manufacture, August 2004, pgs. 26-29.
39. Eric Bogatin, “Skewering Skew,” Printed Circuit Design & Manufacture, April 2005, p. 48.
40. Russell Dudek, Patricia Goldman and John Kuhn, “Advanced Glass Reinforcement Technology for Improved Signal Integrity,” Printed Circuit Design & Fab, February 2008, pgs. 40-42.
41. Scott McMorrow and Chris Heard, “The Impact of PCB Laminate Weave on the Electrical Performance of Differential Signaling at Multi-Gigabit Data Rates,” DesignCon East 2005.
42. Charles Pfeil, “The 0.8 mm Pin Pitch BGAs, Part 1,” Printed Circuit Design & Fab, September 2008, p. 48.
43. Syed Wasif Ali, “BGA Escape/Routing Patterns for Fine-Pitch Devices,” Printed Circuit Design & Manufacture, August 2007.
44. “Ultra Low Voltage Intel Celeron Processor in 5.25-inch Form Factor,” Intel White Paper, October 2003.
45. “Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements,” JESD51-11, June 2001.
46. Henry W. Ott, “PCB Stack-Up Part 5,” Henry Ott Consultants, 2002.
47. Zulki Khan, “Improving Fabrication Yields by Design,” Printed Circuit Design & Fab, April 2008, pgs. 24-26.
48. Martyn Gaudion “Controlled Impedance Test,” The Board Authority, September 2000, pgs. 56-60.
49. Abe Riazi, “TDR for Differentia Pair Characterization,” Printed Circuit Design & Manufacture, September 2005, pgs. 17-18.
50. Charles Grasso, “Measuring Printed Circuit Board Characteristic Impedance Without a TDR,” Douglas C. Smith High Frequency Measurement Web Page, Technical Tibdit, Feb. 2004.
51. Abe Riazi, “TDR for Differential pair Characterization, Part 2,” Printed Circuit Design and Manufacture, December 2005, pp. 30-31.
52. Eric Bogatin, “A High-Bandwidth Probing Plan,” Printed Circuit Design and Manufacture, March 2004, p. 18.
53. Geoff Lawday, David Ireland and Greg  Edlund, “A Signal Integrity Engineer’s Companion,” Prentice Hall, 2008, pp. 204-208.
54. Alan Staniforth and Martyn Gaudion, “The Effect of Etch Taper, Prereg and Resin Flow on the Value of the Differential Impedance,” Application Note Ap148, Polar Instruments Ltd., 2002.
55. Steve Monroe and Otto Buhler, “The Effect of Etch Factor on Printed Wiring Characteristic Impedance,” 11th Annual Regional Symposium on Electromagnetic Compatibility, Oct 3, 2001.
56. Roy G. Leventhal and Lynne Green, “Semiconductor Modeling For Simulating Signal, Power, and Electromagnetic Integrity,” Springer 2006, pp. 246-247.
57. John Coonrod, “Processing High Frequency Materials, Part 2,” Printed Circuit Design & Fab, April 2009, pp. 40-43.
58. Vikas Shukla, “Signal Integrity for PCB Designers,” Reference Designer Inc., 2009, pp. 28-29, pp. 154-155.
59. Abe Riazi, “PCB Stackup Design – Key Parameters, Tools and Methodologies,” presented at Broadcom, Irvine, California, March 26, 2009.

DR. ABE (ABBAS) RIAZI is a senior staff scientist hardware development with Broadcom Corporation in Irvine, California. He can be reached at This email address is being protected from spambots. You need JavaScript enabled to view it..

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