LYON, FRANCE – The volume of devices packaged using flip chip technology will double from 16 million wafers per year in 2014 to 32 million wafers per year in 2020, reaching $25 billion, says Yole Développement.

Expected growth is supported by the wider adoption of Cu pillar technology, as well as Moore’s law pushing beyond the 28nm node and “More than Moore” evolution in DDR and 3D ICs, according to the research firm.

Demand will come from mobile, wireless, LEDs and CMOS image sensors, as well as from consumer applications, such as tablets, smart TVs, set-top boxes, and computing, and high-performance/industrial applications, including networking, servers, data centers, and high-performance computing.

Yole expects steady growth for traditional ICs such as CPUs, GPUs and chipsets for desktop/laptop applications, which were early adopters of flip-chip technology.

Gold-plated wafer bumping will grow, driven by demand for IC display drivers for 4k2k ultra-HD TV and high-resolution and large screens for tablets and smartphones. Yole expects capacity to expand at a CAGR of 4%, from 4.3 million to 5.4 million wafers from 2014 till 2020.

The firm expects a slight decline in gold stud bumping capacity, from 304,000 to 293,000 from 2014 to 2020, mainly due to radio-frequency devices moving from flip chip to wafer-level chip scale package. However, emerging applications such as CIS camera modules and high-brightness LEDs will increase demand for stud bumping.

Intel has recently qualified ASM’s high throughput TCB bonder for assembly of 14nm chips for their CPUs in applications such as data centers, servers, and high-end computing. The firm estimates flip chip bonders’ total market value will reach $435 million in 2020, a CAGR of 7%. Flip chip bonders and underfill materials will be key in coming years, Yole says.

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