DARMSTADT, GERMANY -- CST tomorrow will host a free webinar on constraint driven co-design of chips, packages and printed circuit boards.

Memory interfaces have single-ended data rates in the 1GHz-plus range and serial links are running upwards of 10Gb/s. A precise analysis of each of these signals is required at silicon, package and board level. The design and optimization performed on each one of these interconnection levels must be done in a global context.

The webinar proposes a global methodology which combines three dimensional (3D) electromagnetic (EM) analysis for PCB and package with chip power switching macro-modeling.

Differences between a segmentation approach (where silicon, package and PCB are analyzed separately and then combined with standard cascading technique) and an integrated/global approach (where chip, package and PCB are analyzed as single entity in a co-simulation mode) are discussed, and based on the results, guidelines are outlined.

The webinar takes place Dec. 6 at 8 am Pacific, 11 am Eastern. For details and registration: <http://www.cst.com/webinar/12-12-06~/?utm_source=cst&utm_medium=email&utm_content=chip&utm_campaign=2012series>

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