SANTA CLARA, CA – Cadence is accepting abstracts for CDNLive Silicon Valley, which will take place Apr. 11-12 at the Santa Clara Convention Center.

Suggested topics include mastering advanced-node design challenges; addressing automotive design requirements; accelerating SoC integration with Interface IP; software-driven verification; designing in DDR memory; analog/mixed-signal SoC verification; simplifying functional verification with verification IP; PCB design for manufacturing and testability; PCB high-density interconnect (HDI) and flex designs; silicon photonics; low-power design and verification considerations; digital design and full-flow correlation, and vision processing.

To submit an abstract, visit

The deadline for abstracts is Jan. 27.


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