RedHawk version 2014 power integrity software offers distributed machine processing (DMP) capabilities capable of a reported three times improvement in memory footprint,

enabling the simulation of more than 100 million instances or over 2 billion nodes, while maintaining flat simulation accuracy. Leverages increased processing power and memory capacity available in a private machine cluster to simulate each module within the context of the entire chip, including package and PCB elements. To meet sign-off quality, system-on-chip (SoC) dynamic voltage drop analysis requires a flat modeling framework to accurately predict current flow inside tightly coupled elements across chip, package and the printed circuit board (PCB). Due to the global nature of power delivery network, a more traditional hierarchical approach cannot deliver the accuracy needed for sign-off. Features RedHawk-CPA integrated chip-package co-simulation and co-analysis software which maps package to die layout, through pin-to-pin physical connectivity -- seamlessly merging a fully distributed package parasitic network with an on-die power delivery network. By incorporating both chip and package layouts in the same simulation environment, RedHawk-CPA provides immediate feedback on the quality of the package design, as well as the impact of package parasitic on the chip's performance. Is foundry certified for IR-drop and EM analysis for the latest process technology. Supports advanced EM rules that consider current flow direction, metal topology and via types for both power and signal nets. In addition, this release enables thermal-aware EM analysis by providing chip thermal model (CTM) that accurately captures the thermal distribution that is critical for FinFET devices with greater self-heating issues.

Ansys, www.ansys.com

• Prev
• Next