TimingDesigner 9.4 is integrated with Cadence Allegro Sigrity SI solution to provide highly-automated timing closure environment for DDRx interface design and sign-off. 

Can automatically export cycle-accurate timing simulation results to TimingDesigner for graphical viewing and analysis. Combines power-aware sign-off-level simulation accuracy with parameterized timing diagrams. Displays data in a visual format. Can identify potential problems in context and make on-the-fly adjustments to test potential solutions before re-simulating or making a change in implementation. Provides DDRx interface documentation showing timing margin between all critical interface signals.

EMA Design Automation, www.ema-eda.com

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