CR-8000 2013 includes upgrades to System Planner and Design Gateway.

System Planner now includes  functions for studying behavior, signal quality and 3D space constraints. Streamlines design flow for real-world engineering design, with embedded multi-board SI analysis. Studies behavior and signal quality of system-level interconnections during early design planning stage. Allows "what-if" analysis to capture optimal topology and termination schemes. Imports accurate 3D enclosure and component models, for creating board outlines, viewing component profiles, and automatically generating mechanical constraints (such as height restrictions) for multi-board floor planning. Enhanced design reuse supports drag-and-drop of logical and physical data from the reuse library, which then can be fed directly into the design flow with Design Gateway (logical design) and Design Force (physical design).

Design Gateway includes improvements for hierarchy, rule checking, and an Intel Schematic Connectivity Format (ISCF) format for Intel design review. release, help design teams under tight deadlines reduce design iterations and deliver products to market faster. Stencils, a library of predefined shapes and profiles for logical, physical, and parametric planning, now offer improved support for power signals.

Design Gateway's Circuit Advisor, part of the schematic engineering environment, includes new rule checks to support multi-board design for physical connector mismatches, I/O checks to ensure proper continuity between boards, and checks for duplicate references throughout the system. Simplified classification of nets and constraint entry eases definitions of complex spacing requirements for high-speed interfaces such as PCI Express and DDR2/3/4. Includes  support for ISCF, enabling customers to send design schematics to Intel for review to ensure that their chip sets are implemented properly to meet specifications.

Zuken, www.zuken.com

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