Cadstar FPGA combines the Active-HDL Lite verification tool and the desktop PCB design suite. Performs mixed language simulation for FPGAs. Is structured on integration of FPGA design within the PCB layout. Uses Design Flow Manager. Said to provide one universal project manager that controls all design files for simulation, synthesis, place and route and pin assignment to the PCB. Supports I/O synchronization.
 
Zuken Ltd, www.zuken.com
Aldec Inc., www.aldec.com

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