SANTA CLARA, CA – Sigrity Inc. introduces OptimizePI, a next-generation power delivery system (PDS) solution that is said to be the first to provide minimum-cost decoupling capacitor selection and placement to achieve desired PDS performance.
 
This new solution is based on Sigrity’s analysis and verification capabilities for the entire PCB and IC package structure. It reportedly allows designers to assess PDS performance against design specifications, make interactive “what if” decap placement and selection investigations, minimize decap cost for specified PDS performance and judge performance vs. lowest-cost tradeoffs.
 
OptimizePI considers both component and manufacturing costs during its automated selection and placement of decoupling capacitors. Its use reportedly results in significant cost savings, both through component count reduction and selection of lower-cost capacitors, with no degradation of PDS performance. Using OptimizePI, it is said that designers can recapture the PCB or IC package area for unnecessarily placed decap pads and vias.
 
Jiayuan Fang, president of Sigrity, said “Our customers tell us that, until now, power integrity tools did not explicitly consider design cost or optimization, forcing them to ‘best guess’ decap placement in their designs, or resort to over-designing. OptimizePI relieves them of this burden and the costs of unnecessarily robust performance. It helps them make effective business-level decisions and results in significant cost savings for their companies.”
 

 
Reported PADS2007 enhancements include:
 

• High-speed routing improvements – Controls for matched length nets and differential routing improvements.  
  
• Square and chamfered corners, DXF-in import and via matrixing enhancements for RF design.
• Blind/buried via drill table improvements – Designs with partial vias (blind or buried) are automatically updated with the layer pairs and drill count of the partial vias in the design.
• Alphanumeric pin improvements – Simplifies creation of large BGA-based parts.
• ECO enhancements – Includes comparison of design rules between the schematic and layout databases.
• Design for fabrication (DFF) analysis – Powerful fabrication checks, such as acid trap, starved thermals, solder mask slivers are checked in the CAD environment and database, allowing the designer to identify and correct manufacturing problems in PADS Layout, before Gerber generation.
• Pin number visibility – The user has the ability to turn on/off the visibility of the component pin numbers, either numeric or alphanumeric, improving designer productivity during routing.
• SI analysis – Integration of DxDesigner and the HyperLynx LineSim tool through a new interface allows fast transfer of a circuit for analysis and back annotation of termination resistor values.
• Analog simulation - Provides a board level simulation analysis and verification through a common schematic editor for both simulation and PCB design entry.
  

 "Mentor Graphics continues to invest in the future of PADS by strengthening the capabilities of designers to integrate RF circuitry design, high-speed net analysis and routing, and DFF into the PADS design flow," said Dan Boncella, director of marketing, System Design Division, Mentor Graphics.

CONCORD, CA – March Plasma Systems has released an improved PCB panel pre-etch conditioning technology. With it, the company's PCB series products can reportedly increase the throughput in applications such as desmear and etchback. It is said that productivity improvements of more than 30% can be achieved with this new system enhancement. The new product feature will be implemented on all new PCB series shipments, and is also available for retrofit on existing systems.

The typical three plasma process steps required for high uniformity treatment in desmear and etchback applications include a pre-etch segment, a desmear or etchback segment, and a residual reactant removal segment. The PCB panel pre-etch segment is required to ensure controlled etch across each panel within an individual processing cell as well as from processing cell to processing cell. The new pre-etch conditioning technology reportedly reduces this segment's time by more than 65%, resulting in improved PCB system throughput.

WILSONVILLE, OR – LPKF’s MicroLine UV 3000 is a compact laser system designed to cut precise openings in polyimide coverlayer foils and to cut flex circuits. It reportedly reduces product changeover time.
 
The MicroLine UV 3000 contains a new high speed linear drive for flexible circuits, featuring greater positioning accuracy, higher speed and faster acceleration resulting in reduced processing times. It is said to encompass tools with the ability to perform precision cutting, routing, skiving, drilling, cutting pockets, structuring of etch/solder resist, micromachining of ceramic substrates and more.
 
Vice President of Sales Jim Greene said, “These capabilities noticeably reduce changeover time, making it an efficient component of any fabrication process, especially where physical space is a premium.”