It might be time for a 50-year-old concept to catch on in PCB fabrication.
Back in 1978, at the first Printed Circuit World Convention in London, the proceedings described a novel additive technique for producing printed circuit boards on epoxy glass-based laminate. It was a complete contrast to the subtractive approach that was typical at the time and still dominates today. Now, as we strive to achieve ever finer circuit geometries, and sustainability of manufacturing processes has become a prime concern, additive processes could offer a way forward.
Among the most intriguing applications I’ve seen, 3-D printing of twisted-pair interconnects is unlikely to be adopted as a high-volume manufacturing technique but could prove extremely useful for maintenance and repair.
On the other hand, additive technology is set to have a huge impact on advanced IC packaging and, particularly, high-density substrates. This is a fast-moving area, currently transforming through demand for broadband 5G services and AI acceleration, all the way from energy-conscious edge devices to high-performance computing in the cloud. Processor packaging trends are driving demand for high-density, thermally efficient substrates, where additive technology is making the difference.
As we seek smaller chip geometries and better thermal performance, glass is emerging as a stable substrate material with excellent electrical properties. It’s inherently suited to additive circuit fabrication and permits line/space resolutions as fine as 2μm, which is difficult using traditional subtractive methods.
Working with glass presents its own challenges, however. Through-glass vias (TGVs) tend to crack and chip during production. Controlling the via shape is both difficult and critical, as any distortion can compromise subsequent metallization. Overall, process control and volume scalability are underdeveloped compared with through-silicon via (TSV) technology, which is much more mature.
Commercial 3-D ICs have used TSVs for more than a decade. Process flows are well-established, issues such as thermal cycling, electromigration and mechanical stress are understood. There are proven failure mitigation techniques, such as stress buffers. A robust ecosystem like that for TSV metrology, inspection and simulation has not yet been developed for TGVs.
On the other hand, organic substrates are now struggling to support finer feature resolution. Challenges such as surface roughness, dimensional instability and the presence of process residues and natural defects hinder progress and negatively affect yield.
Hybrid glass-organic composite substrates combine the electrical and dimensional stability of a glass core with the flexibility and manufacturability of organic build-up layers. Different approaches become available, including using the glass as a passive core that remains undrilled and serves solely as a mechanical and thermal backbone, displaying low CTE and excellent electrical insulation. In this case, only the build-up layers have vias, avoiding the complexity and risk associated with TGVs.
Alternatively, by taking that risk and creating vertical interconnects through the stack, the glass becomes an active interposer. Although this adds significant manufacturing complexity, routing through the glass facilitates applications like 2.5-D chip assembly and high-density chiplet packaging.
Some cutting-edge substrates adopt a hybrid strategy to balance performance, cost and manufacturability. TGVs support power and ground delivery through the glass, while organic vias handle signal routing in the build-up layers. Challenges include ensuring reliable adhesion and thermal compatibility between the glass and organic layers. New tooling and inspection methods are necessary, and the cost remains higher than traditional organic substrates, although it will likely decrease with scale.
Composite substrates play a vital role in new chiplet-based IC architectures that combine modular silicon dies packaged together to form complete systems. This approach offers a multitude of possible benefits. Each die performs a specific function, such as CPU, GPU, I/O or memory, allowing chipmakers to create new or custom configurations relatively quickly and at low cost. Yield improves, and heterogeneous integration becomes possible, combining chips fabricated at different process nodes for optimal performance, properties and cost.
To realize these benefits, designers need ultra-dense, high-speed interconnects that organic-only substrates cannot achieve. Hybrid glass-core substrates enable significantly higher interconnect density, and support significantly more chiplets in the same package area, making them a critical enabler for future generations of AI and HPC processors and communication ICs.
They are also shaping the future of panel-level packaging (PLP), enhancing dimensional stability and minimizing warpage, as well as enabling co-packaged optics (CPO) where optical transceivers are embedded in ASICs. These devices transform the performance and power efficiency of equipment for data centers, AI clusters and high-speed switches.
Amid all this, IC substrate technology is associated with some of the most exciting action in the PCB industry today. Indeed, the world’s largest PCB manufacturers are seeing this side of their business grow by as much as 50% and are investing heavily in equipment and know-how.
There is no doubt that PCB substrates and circuit-fabrication processes have come a long way as the electronics industry has developed into the diverse, multi-billion-dollar global industry we know today. In that time, we have etched and ablated away many tons of fresh copper to create the desired interconnects. There has always been an element of additive anarchy, manifested in that early example presented at PCWC nearly 50 years ago, which urged us to consume only what we need. With advanced chip packaging, the application may have finally arrived that will enable additive circuit fabrication to transition from undercurrent to mainstream.
Alun Morgan is technology ambassador at Ventec International Group (venteclaminates.com); This email address is being protected from spambots. You need JavaScript enabled to view it.. His column runs monthly.
