When should you use partitions?
Looking at a spread of components on a printed circuit board without any connections complete can be intimidating. Where does one start?
That question was too much to answer for one of my colleagues back in the day. He was a deer in the headlights, unable to move forward after placing both sides of the board.
The board in question, called the integrated module, was intended to replace a collection of five boards with various functions. It was a 10-layer, double-sided HDI board at a time when HDI was not yet a common thing. It was the most complex board for the company up to that point (Figure 1). One of the evergreen rules of a startup is to do whatever you must to succeed.
Figure 1. The main logic board for a Samsung Chromebook Pro, circa 2018, is a six-layer reference board using 1-N-1+ stack-up technology. We basically get a second layer of microvias from layer 2 to layer 3 using only two lamination cycles. The 45° twist for the CPU helped the DDR length, matching and looked cool on the monitor. Show me an edge and I’ll show you a connector! The diagonal orientation gave a longer runway on each side. The sides facing the two memory chips use topside routing. Making the connections would be easy compared to tuning the data and address groups. It’s nice to have multiple layers in play, providing immunity for each lane.
Keeping codesign on track in the early stages of routing. The lead engineer asked if I could help out. We worked out a plan where I showed up at 4 a.m. and worked until 1 p.m., when Robert would take over and work until 10 p.m. My part was layers 6-10, while he covered the top five. Understand that the two of us and others came from a team that did nothing but single-layer RF amplifier boards with a solid aluminum pallet as the second layer.
What do you do? Maybe give the autorouter a chance to connect the ground pins with a microvia-in-pad to the adjacent layer. Look at the results as a sanity check. Improve the fanout manually where it went astray. By fanning out the ground net, approximately 20% of the pins get hooked up. Get a snack and mull over the next step with the voltage regulators while reusing every possible circuit as inspiration. That was my plan. I’m not above using shortcuts to get me to the next coffee refill.
Back to work. Connect the RF traces that could be done on the surface layer, routing from point to point. Plan for the ground pour and shepherd vias that will shield the analog traces and surround the RFIC. Take that space, then try to preserve the buffer area as much as possible. Coexistence doesn’t happen by chance.
Bring in the power on traces just thick enough to do the job without excessive radiation. Even narrower spurs will extend toward the designated capacitors and their pins (Figure 2). The power delivery network was courtesy of Occam’s razor while feeding fields of pins. In some cases, such as RF, less is more.
Figure 2. The Rockchip RK3399 “gets it” as far as the power delivery is concerned. The ball map has two power pins next to two ground pins. The power pins can be joined through a single via, same with the ground, and then an SMD 0201 capacitor dropped between those two vias on the far side of the board. The chip has this arrangement over and over, which simplifies placing decoupling caps. The DDR is decent too, with almost all the data and address pins on the outer two rows for via-less routing of most of the two DDR memory chips. The Rockchip is a 17 by 17mm package with 0.4mm pitch.
The “last mile” of the power domain really was one of the tricky areas. We had to work out the star-routing to the power pins, where a single cap is responsible for more than one power pin, while three caps are dedicated to a single pin. Optimizing power to analog devices means using the least amount of copper to get the job done.
That kind of specificity was difficult to capture. I learned all about net scheduling so I could drive the rats nest to maintain a line between the designated cap and power pin. To keep track of the plan, the highlight command was used not for the net but down to the pin level, matching the pin on the capacitor to the one on the RF amplifier.
The color code meant that we both knew the routing intentions. The schematic noted the associations and served as the source for this information, including a power tree that diagrammed the grid by domain and showed how many milliamps to deliver to each pin. From there, the width of the copper is calculated using the famous IPC chart, which was already an old friend back in the 1990s!
Now, with power squared away, let’s get on those non-critical connections that could be done on the designated layers. Finally, several nets reached both sides, so when everything on layers 6-10 was good, I started dropping vias where required, letting Robert take it from there.
There may have been a little more back and forth between shifts, but working that way, we reached the finish line. Partitions might have been nice; they work by area, not layers. This was the late 90s, so that wasn’t an option.
Serial or parallel PCB design flow? No matter the decade, teamwork isn’t quite as efficient as a solo effort, but it does compress the timeline. I’ve used the same method with service bureaus over and over again. I’ve also been the swing-shift consultant, showing up at 4 p.m. Keeping the vendor hemmed into a specific area has value. A section within a shield or an area that uses high voltage design considerations might be farmed out to a service bureau.
This is just my opinion, part of which comes from this early work-sharing experience. Keeping the board whole and working around the clock is more efficient than breaking the board up into two or more pieces. The size of the board might influence this choice, though.
While a partition is checked out, the owner of the rest of the board has to manage that boundary with care. Reinserting the new circuit for the old can take time if the old stuff isn’t properly cleared out. I prefer serial design to parallel for the types of boards I’ve done. Parallel design might work better if all the designers are under one roof and on the same shift.
The HDI decision guide. A through-hole solution was always available until the chips went mobile and shrank below 0.65mm pitch down to 0.5mm and further with each generation. The 0.65mm devices are the last node supported with normal vias. From there on, we use microvia-in-pad techniques.
The 0.5mm node is interesting. Just as we measure silicon in nanometer gate size, marketers promote IC packages by their pin pitch. And 0.5mm is at the crossroads of routing a trace between vias and digging deeper into the board using the z-axis to escape the package. Welcome to the HDI barrier. At the root, the problem is the good old via.
Figure 3. This 12-layer plated through-hole (PTH) board served as proof that via-in-pad using through-hole vias is a bad idea. It took a redesign, clearing out all the connections for the FPGA at the top of the board. The fan-out retained the through-hole vias, while space was allocated for the capacitors by sharing vias between the DC pins.
Staying a step ahead of the DfM monster. PCB fabricators are “disinclined” (severe understatement) to plate a through-hole within the surface mount pads. When they do it anyway, the assembler is likely to register a complaint for yield issues during reflow soldering. Turning a through-via into a solderable surface is harder than sequential lamination. Combine that with stacking microvias, and the real estate cost of a via goes away until it reaches the 0.35mm node.
(If you’re wondering, solder mask-defined lands are used anywhere below 0.4mm, and even that is debatable. About 60 designers who applied for a job at Google know what I’m talking about. Interviews came in waves, so I was ready with standardized questions. It felt like a huge responsibility, to be honest.)
Where were we? Typical solder mask limits are enhanced with laser-defined lands. Laser beams don’t get dull or lose their strength over time, but they do take some time. When it comes to silkscreen, it’s still nice to have a laser printer so the little text can be read under a microscope. These precision operations cost more than screen printing. These decisions must be made in concrete, upfront, and take the form of a statement of work. The SOW, along with the PO, drives the action. One of the norms of working with an outside vendor is the requirements are well-defined. They will accept your potential revision while adding an ECO fee. Ouch!
By definition, HDI will result in more congested boards, where the silkscreen may not be able to identify every component. The first element to go is the component outline when the space between parts doesn’t support it. Then, the reference designators can be strategically eliminated where small parts are clustered. The thing we want most to preserve is the polarity marking for diodes, and similar safety information. Boards or assemblies too small to mark could use the bag-and-tag inventory method.
Beyond the artwork, the deliverables on the design for manufacturing front include:
- Drawings with notes that describe the finished board in both the bare and assembled states
- Include a table with stackup information weighed against impedance callouts, giving purpose and meaning to the layers and line widths
- X-Y coordinates for placement of components and test points
- Netlist and bill of materials.
Some ODMs ask for the ECAD database. Say no, or go to File > Properties and lock the design with a password and set permission to View Only.
Build confidence in the vendor with small victories. Instead of doing non-metal work yourself, outsource it. I have no problem sharing the housekeeping work with a contractor. The fab drawing may need dimensions or other details. The assembly drawing and silkscreen could be organized ahead of a placement review. Shed a few of these mundane tasks as an icebreaker before cutting them loose with the general-purpose routing.
An in-house PCB designer is preferable if you have the infrastructure. Quite likely, it’s a remote situation out of necessity. My key vendor has a local bureau in Silicon Valley and an overnight team working their normal day shifts in Taiwan.
Figure 4. The fanout is complete, and the critical nets are routed along with most of the power domains, particularly for the primary components, where the tough compromises are made. The guideline for the remaining routing is to stay out of the way of the existing circuits. This is a point where you can take a good weekend off and let the team carry the ball.
Happy hour: A daily standup meeting before going home. On day one, there is a full-on PowerPoint slide show with a few slides enumerating the design goals. Every weekday morning, the board comes back from the after-hours team, and we review their progress while they’re at home. We may or may not have created a partition for the local bureau to work on during the day.
Either way, before going home, we would add more screen caps and instructions to PowerPoint. The afternoon handoff could be the only time we could read in a new netlist. We gave them the whole board to work on at night and on weekends. Unless you have a hierarchical schematic, the logic is frozen while partitioning the layout. When “happy hour” came, we consolidated the board and imported new logic, doing placement if necessary. Those with schematic improvements had to wait for that window or be there with me at 7 a.m. That’s one of the big strikes against partitions.
Every morning was like Christmas. Open it up and find what you have. Compare what came back to what was requested and do any course correcting with more slides. When the service bureau takes over at the end of the day, certain layers will be turned on, nets highlighted, and rats nests enabled. That’s their hill to climb. These visible clues can be given daily, even if no other work was completed in-house. Like on Christmas.
Managing expectations. The expectations will be as clear as we make them. Even so, we might get a laugh at the next morning’s results. Sometimes, that would define a new PowerPoint slide, and other times it would mean a refresher on an older course correction. When it’s the latter, it validates why I use a slideshow to document the details of a design that employs more than one designer.
The first step in outsourcing is to establish a nondisclosure agreement (NDA), followed by setting up a purchase order for a specified number of hours on demand. You start making phone calls and sending emails when the job in front of you has more content than the calendar provides. We judge not by the color of the mask, but by the content and calendar. It’s good to have that help on tap before you need it. Stay ready, my friends.
John Burkhert, Jr. is a principle PCB designer in retirement. For the past several years, he has been sharing what he has learned for the sake of helping fresh and ambitious PCB designers. The knowledge is passed along through stories and lessons learned from three decades of design, including the most basic one-layer board up to the high-reliability rigid-flex HDI designs for aerospace and military applications. His well-earned free time is spent on a bike, or with a mic doing a karaoke jam.
