When the data rate exceeds 3 Gbps in today's high-speed serial links, the digital board design is no longer a simple layout problem but becomes a microwave-engineering problem. Every individual interconnect component requires careful evaluation and characterization before it can be used in a channel. For a successful first-pass design, the high-speed digital designer must establish robust design or constraint rules before deciding the layout of a board. These rules are established by evaluating the single ended or differential S-parameter performance of building blocks of a channel. This could include dielectric stackup, via holes, transmission line width and the spacing of ground clearance via holes at the required data rate and for the required rise time performance.
As data rate goes high in frequency, the channel building blocks can no longer be considered lumped components, but need to be treated as distributed transmission line circuit components. Effects such as dispersion, skin effect, low-pass filtering effect of transmission lines, reflection due to impedance mismatch and crosstalk between adjacent transmission lines dominates and degrades channel performance. These effects are best characterized using frequency domain interconnect models and simulators.
Many of the SPICE simulators that are available have trouble simulating frequency domain models such as S-parameters, and the designer often needs frequency domain simulators to understand behavior of interconnects over the frequency range and to establish robust design rules. The frequency domain simulator produces either S-parameter or voltage and current spectrum at any node as a function of frequency. Without running time domain simulators and post processing the simulated waveform it has been difficult to compare frequency domain simulator output with the digital system specifications that are often defined in terms of eye diagram parameters (such as eye opening, rise time and eye height).
Many EDA software packages, such as Advanced Design System EDA software from Agilent Technologies, allow you to work in frequency and time domain using the same set of component libraries. They can convert frequency domain simulated data to an eye diagram plot to compare performance directly against system specification, and time domain simulated data to frequency domain.
In a simulation tool, eye diagram measurements are necessary to establish high frequency design rules and to validate system performance against design specifications. Establishing a design rule process was somewhat disconnected in the past because designers could not relate the frequency domain behavior of a circuit directly with its eye diagram performance without post processing frequency domain simulated data.
Establishing design rules often requires optimization of the analytical or physical models in terms of its single ended or differential S-parameter performance, but it has always been difficult to use a system specification such as eye height as an optimization goal with various simulators. The current trend is towards integrating the eye diagram measurements as a design tool to establish high frequency design rules.
Consider the simulated waveform of an interconnect, as shown in Figure 1. It is difficult to characterize this output waveform quantitatively in terms of logic level 1, logic level 0, rise time and fall time because of its statistical nature and performance variation over bit patterns.
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The eye diagram of this waveform provides a convenient way to characterize this waveform. The eye diagram plot is created by slicing the long waveform into unit-interval-long sections and constructing unit-interval-wide time shifted overlay plots. The eye diagram plot provides a qualitative and quantitative description of system performance and allows the designer to decide if the transmitter or interconnect performance is acceptable at the receiver end or if it requires special signal processing techniques to recover the digital signal.
The eye diagram is characterized by slicing it into small bins and calculating the statistical distribution of a number of traces passing through each bin. The statistical distribution allows the designer to calculate eye parameters such as logic level 1, logic level 0, eye opening, rise time, fall time, eye width, eye amplitude, signal-to-noise ratio and jitter.
Time delay is an important parameter used in creating eye diagram plots from simulated data. It defines the value of the delay used to acquire a starting sample of the voltage waveform and influence the eye crossing points on the timing axis. The required time delay can be determined from the statistical distribution of sub region, (Figure 2). The comparison of the mean value of the horizontal histogram created in the region against the center of unit interval provides the required time delay.
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The majority of the eye parameters are based on statistical distribution of traces within 40-60% of the region located in between eye crossing points. This makes it essential to identify the eye crossing point first, before any other parameters can be determined. The crossing points are determined by calculating the statistical distribution in a vertical narrow strip along the timing axis, followed by the statistical distribution across the amplitude axis. The mean value of the horizontal histograms determines crossing point on the time axis value, while the mean value of the amplitude histogram created at crossing time points provides a crossing point on the voltage axis. The statistical distribution within the 40-60% region within the eye crossing point for the top and bottom half of the eye diagram provides logic level 1 and logic level 0. Other eye parameters can also be calculated from this distribution.
An ideal eye opening would be measured from the 1 level to the 0 level. However, noise in the system will cause the eye to close. The eye height measurement determines eye closure due to noise.
Signal-to-noise is a ratio of the signal difference between level 1 and level 0 relative to the noise present at both levels. Signal-to-noise is similar in construction to a Q-factor measurement.
Eye width is a measure of the horizontal opening of an eye diagram. Ideally, the eye width would be measured between the crossing points of the eye. However, jitter may appear on the waveform and influence the eye opening. To compute eye width, the crossing points first are located and then a vertically thin measurement window is placed horizontally through the crossing points. The data within this measurement window is analyzed.
Rise time is a measure of the mean transition time of the data on the upward slope of an eye diagram. The data crosses through the following three thresholds: the lower, middle and upper thresholds, as well as through the eye crossing point. A histogram is first constructed to find the mean location of the crossing points relative to level 1 and level 0 position. Histograms are then constructed at each of the three threshold levels (e.g. the 20%, 50% and 80% points on the transition). The histogram mean at which the data crosses the separate threshold level is determined. The time difference between the 80% and 20% crossing point determine the rise time performance.
The horizontal histogram across X-axis across crossing point provides the peak-to-peak jitter performance. The statistical standard deviation of jitter histogram provides the RMS jitter performance only for cases where there is random jitter content present in the signal. All of these eye diagram measurements are automated in the eye diagram interface in Agilent's Advanced Design System, as shown in Figure 3.
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The waveform in Figure 1 is the simulated waveform of a differential channel operating at 15 Gbps. Here the channel is represented by S-parameters for its insertion loss and return loss properties as a function of frequency. Designers can use time domain simulators such as high frequency SPICE from Agilent Technologies to look at its eye diagram performance. Often the channel is a passive interconnect model, as in this case, and one could also use a frequency domain simulator such as an AC simulator to characterize its performance in time domain. The frequency domain simulator provides a fast and convenient way to determine the eye diagram performance of a channel with a bit sequence source of limited length and avoid convergence issues. The length of bit sequence, the data rate, and rise and fall time of the bit sequence source determines the start, stop and frequency resolution for AC simulation (Figure 4). The simulator output is converted to a time waveform using the Inverse Fast Fourier function ts( ), and all the eye diagram parameters are measured.
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One way to optimize interconnect performance is to measure eye parameters during simulation by defining eye measurement equations on the schematic page instead of the data display, or as post processing steps. Calculating eye parameters during simulation enables the designer to optimize the interconnect for eye measurements and help create high frequency design rules.
At high data rates, the equivalent circuit of a transmission line is represented by distributed series inductances and shunt capacitances. The equivalent circuit represents a transmission line behaving as a low pass filter and the circuit attenuates the high frequency contents of a digital signal. The highest frequency content in a digital signal is present in the edge portion of the waveform. It is the rising and falling edge of a digital waveform, which is affected the most by the frequency dependent behavior of the transmission line. Filtering of high frequency components in a channel degrades BER performance of a digital signal and limits its data rate. For a channel with a limited eye opening, the BER performance can be improved by using a passive equalizer at the receiver end. The passive equalizer is usually a high pass filter and provides an inverse slope compared to channel response. It attenuates low frequency content in a digital signal and passes high frequency content with minimum attenuation. When cascaded with a channel, it flattens insertion loss response over the frequency band. The side effect of using a passive equalizer is the decrease in signal amplitude and a requirement for a broadband amplifier. If the eye is totally closed at the receiver end, passive equalization cannot be used and adaptive equalization (such as Decision Feedback Equalization) is the only choice available to designers to maximize the eye opening.
Figure 5 shows the equivalent circuit of a passive equalizer used in this design. When the channel is simulated with this equalizer, the eye diagram performance is improved, but we realized that there was more we could do to maximize eye diagram performance. Instead of tuning the individual parameters of the passive equalizer, we set up an optimization goal to maximize the eye opening from 0.69 to 0.9 using a random optimizer.
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For the channel, we used the AC simulator to analyze channel performance in frequency domain but characterize the simulated data in time domain, and performed eye diagram measurements and optimization.
Until now, time domain optimization has been practically impossible to perform due to the difficulties in defining optimization goals. Any change in a reactive or distributed element will change the flight time and negatively affect any optimization goal if defined with respect to time. This is not an issue when dealing with eye diagram optimization using the setup shown in Figure 6, because any change in the flight time is accounted for with automated delay and crossing point calculations to determine the 40-60% region within the eye crossing point. We have not defined an explicit time parameter anywhere in the optimization goal because the eye diagram measurement equations automatically calculate all the eye diagram parameters with data rate defined. We achieved frequency domain simulation, and time domain characterization and optimization of a digital signal. This technique is going to play an important role in the future to help design high-speed interconnects and to open doors to optimizing the BER performance of digital system and interconnects.
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In this article, we demonstrated eye diagram optimization using frequency domain simulation but this technique can be used with time and numeric domain simulators as well as to analyze and optimize serial link and to establish high frequency design rules. PCD&M
Sanjeev Gupta is an applications engineer with Agilent Technologies EEsof EDA division. He can be reached at This email address is being protected from spambots. You need JavaScript enabled to view it.. Gunnar Boe has been an application engineer with Agilent Technologies since 2001.
The authors acknowledge the significant contributions of John Olah from Agilent Technologies, EESof EDA division in implementing eye diagram measurements and optimization in Advanced Design System.