Assumptions can be costly, so communication is more critical than ever.
It's important for OEMs and EMS providers to understand the many factors that affect multilayer board fabrication. Multilayer boards once averaged fewer than six layers, but now normally start at four layers and go up to 40 and even more. PCBs currently come in a variety of different sizes, shapes and forms.
The process of fabricating multilayer boards is more challenging than for single- or double-layer boards simply because multilayers involve many highly definitive steps and processes. There are seven or eight fabrication stages, and each must be properly planned and executed. Each stage has a high probability of having different issues, and each issue has different implications, thereby minimizing output or board yield.
Fabrication note placement is the first hurdle. OEMs are usually vague in their note placement and callouts for various reasons. Other related problems deal with hole charts, stackup information, material callouts and board thickness. In some cases, the lack of detail stems from inexperience or plain carelessness. Consequences can be costly, especially from a time-to-market perspective. For example, a two-day quickturn board fabrication with poorly outlined fabrication notes can put the project on hold until the OEM correctly addresses those issues.
Stackup is of particular importance in high-speed designs because it determines a board's impedance control specifications. Impedance controlled traces are required to keep the signal clean and clear and to suppress noise and crosstalk. Here, a trace is sandwiched between two ground planes to suppress noise. Unless stackup is properly defined, the finished product may not get the impedance within the 5 - 10% of tolerance the customer expects.
If the OEM fails to provide stackup details, the fabrication house is forced to make assumptions, but it must confirm the details with the OEM. On the other hand, when stackup details are provided, a proper fab note should call out for stackups for any kind of impedance, as shown in Figure 1. It could be single-ended, differential pair, multiple, single-ended impedance on the same layer, or multiple differential pairs on the same layer of the board. The board house needs to incorporate etchback factors and other compensations to give the OEM the impedance it is targeting, which originally comes from stackup information.
FIGURE 1. This shows the stackup of a four-layer board, showing impedance control specifications necessary to fabricate a multilayer board within allowed tolerances.
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Materials
If a specified material is not available at the time of production, there may be an alternate material in stock. This is especially important if the board is a hybrid, one that features multiple materials such as FR-4, polyamide, Rogers or Teflon-based materials (Figure 2).
FIGURE 2. This screen shot shows a detailed list of fabrication notes with important elements incorporated in them to be able to successfully fabricate multilayer boards.
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But there is a caveat. Sometimes in high-speed designs, different versions of one material, like FR408, might have resin construction that differs from supplier to supplier. Substrates are made of fiberglass with different formations of glass inside the laminate, meaning that some manufacturer's products are better suited for high-speed designs than others. For example, although it's the same FR408 material, one material manufacturer may have resins placed in such a way as to make the board extremely unfriendly to high-speed use. Naturally, this problem is many times worse in a 40-layer design than in a four-layer.
For exotic materials like polyamide, Teflon or Rogers, alternate materials become more important. This is because fabrication houses at times do not have these materials in stock and lead times for obtaining them can be three weeks. Repeat runs of the boards after a lengthy period become a major issue, and the OEM cannot get the product in time because he has not called out for multiple materials in the fabrication notes.
One solution to the problem of exotic materials: When the board is in design and layout, either the service bureau or OEM should closely work with the fabrication house and inform the shop of the specific materials required. Although there are a few weeks of lead time involved, the board house knows in advance the specific types of materials needed for a particular board, and there aren't any unexpected surprises in terms of material lead times.
Netlist Verification
Netlist verification is key to successful multilayer board fabrication. OEMs usually provide electronic data to a board house in the Gerber file format. A Gerber file is basically unintelligent data that in effect states that a certain trace goes from point "A" to point "B" and that a given set of XY coordinates coordinate with another set of xy coordinates, and so on. However, sophisticated CAD software packages generate the IPC-356 netlist format, which can be incorporated into any kind of DFM software and the board. When the board is fabricated, it is verified against the IPC356 netlist. This is the only correct way to create a netlist and verify the fabricated board against the IPC-356 netlist.
Sometimes, OEM customers are not aware that the IPC-356 netlist is the golden netlist used to verify board fabrication. In these cases, the fabrication house creates its own netlist by extracting data from the Gerber files, i.e., unintelligent data. In short, when the finished PCB is verified with data that's generated out of the same board, a netlist is created from the Gerber file data, which, in turn, is used to make the board. This test has minimal significance since it is not an industry standard IPC netlist and cannot detect all the errors that might have crept into the board.
As shown in Figure 3, the design rule check (DRC) must originate with the OEM customer and then be addressed at the root level at the OEM location. The reason? The OEM has the database source for those design files. By creating the DRC at the database level before submission to the fabrication house, the OEM assures itself that database integrity is not compromised. It is clean, and all the problems are caught at the source rather than at a later stage when sometimes no options are available. If a board shop catches a mistake halfway through the process, some mistakes may not be fixable. Consequently, the entire project may have to be scrapped.
FIGURE 3. An example of DRC showing the defined DFM constraints as defined by the PCB design engineer for multilayer PCB fabrication.
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Having the right equipment at the fabrication house also assures high-quality multilayer board fabrication. Does it have an AOI machine? How new are their drill machines, routers, scoring machines, etching tanks and test systems? The newer the equipment, the higher the probability is of quality multilayer boards. This equipment must be calibrated according to the specifications provided by the equipment manufacturers. Fabrication houses make changes on virtually every job based on an intimate familiarity with their equipment. Hence, equipment needs to be new and automated so that when technicians insert compensation factors for plating, etching and adjusting copper weight, for example, these processes are minimal.
An AOI machine is particularly vital for inspecting a board's internal layers and making sure there is sufficient clearance in the internal traces. Once all internal layers are laminated, there is no way to inspect the final board, except with a tester. It is best to deploy the AOI machine when internal layers are put together, before lamination. By doing so, errors are caught, sufficient clearance is assured and fab technicians can be sure DRC is performed on internal layers prior to lamination. Without AOI, an internal short or open may be overlooked. More often than not, internal opens and shorts cannot be fixed and the project has to be started from scratch. For this and other reasons, it is important for the fab house to embed a quality assurance step in its process flow sheet to make sure the board is ready for final stages.
Further, chemicals should be analyzed on a regular basis to assure the correct chemistry, which can prevent boards from getting over- or underetched during the etching process. If overetched, traces will be thinner, signal will not be properly carried and if high current is run, it may open the trace. If it's underetched, the trace-to-via and trace-to-copper are shorted. Etchback factors and plating compensations must therefore be done properly. In this regard, it is prudent for the OEM to check a fabrication house's etching and plating processes to determine that the vendor has an in-house chemical lab that conducts analysis on a regular basis.
Outsourcing Processes
It's also important to know which processes a fabrication house performs in-house and which ones are outsourced and how competent those outsourced engineering personnel are. Figure 4 shows a "typical" multilayer board fabrication process. PCB surface finish types such as HASL, immersion gold or immersion silver are some of the common outsourced processes. Sometimes, testing and plating are outsourced. However, it's best to maintain as many processes as possible in-house to have tight control and not need to rely on second, third or fourth sources.
FIGURE 4. Process flow chart showing all the major processes involved in fabricating a "typical" multilayer board.
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But even if these processes are performed in-house, extra care should be taken to verify OEM information and calculations. Smart board shops don't take an OEM's calculations - i.e., those related to stackup thickness for impedance control - as the final word. Instead, they make their own impedance control calculations and verify these against the information provided by the OEM.
Also, when an OEM puts in one order and comes back for the same order six months later, which is considered a repeat order, it is very important for the fabrication house to maintain a stringent documentation control for that particular job to keep revision levels current. Quite often, OEMs call for two, three and even more different revisions of the same product with sometimes very little variations. If document control doesn't maintain proper revision levels, the result can be costly and time consuming - it may cost thousands of dollars and weeks of work to correct these mistakes.
Lastly, an OEM should give a highly complex multilayer board design extra time and not consider it a two- or three-day quickturn. This is especially true of a tight design with 3-5% tolerances for impedance control, multiple differential pairs, and exotic materials. Time-to-market is important, but more important is correctly fabricating such a board, even if it takes five to seven days. PCD&M
Zulki Khan is president and founder of Nexlogic Technologies (San Jose, CA); This email address is being protected from spambots. You need JavaScript enabled to view it.. Phil Lerma is fabrication services manager at Nexlogic; This email address is being protected from spambots. You need JavaScript enabled to view it..
