WILSONVILLE, OR -- Mentor Graphics today announced a new partnership with a handful of component developers based on sharing reference designs and tools via the cloud to accelerate new technology adoption.
The HyperLynx Alliance aims to integrate tools, data and methodology, leveraging the high-speed design and verification tool suite. A so-called virtual lab series, based in the cloud, will build on partner models and reference designs with the HyperLynx tool suite to demonstrate ideal design methodologies to address difficult high-speed printed circuit board SerDes and DDR design challenges. The virtual labs reduce engineering time and costs associated with evaluation design tool requests and design case setup which could take days or weeks. The labs walk through a recommended design process, helping engineers formulate their own methodologies and enabling them to evaluate tradeoffs to improve overall system performance.
Codeveloped with industry vendors, the HyperLynx Alliance virtual labs include the complete HyperLynx design environment, partner IBIS-AMI or S-parameter electrical models, a reference design based test case, and a step-by-step instruction guide. Each virtual lab is free, available 24/7, and designed to be completed within a few hours. They remain available as a future resource for users during real design and implementation stages. Among the first companies to join are Altera, PMC-Sierra, Samtec and eASIC.
The Altera HyperLynx Alliance virtual labs are available free of charge to registered users. Virtual Labs from PMC-Sierra, Samtec and eASIC will be available in early 2015. Users can access any virtual lab via an HTML5 compliant browser.
"We are pleased to be the only FPGA vendor that is part of the HyperLynx Alliance, which provides a great resource to design engineers by allowing them to exchange known-good high-speed design practices and methods," said Raj Patel, senior manager, midrange products, Altera. "These jointly developed virtual labs showcase a number of leading-edge technologies featured in Altera FPGAs and SoCs, like DDR3/DDR4 memory interfaces running up to 2666Mbps and SerDes links operating up to 28Gbps. The virtual labs will help the engineering community quickly gain the expert knowledge required to successfully complete their designs on-time and under budget."
"The HyperLynx Alliance program will provide our customers with push-button and vetted IBIS-AMI simulations, allowing them to rapidly evaluate our SERDES against a variety of industry cables and connectors," added Eric Clement, director of applications for the PMC-Sierra Enterprise Storage Division. "PMC is well known for our industry-leading SerDes, and this Virtual Lab is one more resource to ensure our customers have access to the most comprehensive design methods, tools and technologies."
"Mentor Graphics and our partners are committed to share specific design approaches helping to educate the PCB design engineering community to remove problematic high-speed DDR and SerDes design bottlenecks," said A.J. Incorvaia, vice president and general manager of Mentor Graphics Board Systems Design Division. "Many of today's design teams may be unprepared to meet today's high-speed design issues due to limited experience, design know-how, and immediate access to the latest design software, IC and hardware technologies. The HyperLynx Alliance was created to serve the needs of today's PCB design engineer – with real-time access to tools, technologies and support to remove the uncertainty of today's most daunting high-speed design issues."
