SAN JOSE — Cadence Design Systems has teamed with a top nanoelectronics research institute to launch an automated test solution for 3D stacked ICs.

The collaboration with Belgium-based Imec provides design-for-test (DfT) and automatic test pattern generation technology said to ease testing of 3D-ICs with through-silicon via (TSV) functionality. The technology addresses the test challenges involved with 3D-ICs, which offer increased circuit density and better performance at lower power dissipation in a smaller footprint.

Insights gained during a comprehensive research program on TSV-based 3D-IC design and technology enabled Imec to extend the DfT architecture for conventional ICs with several patent-pending features. The 3D DfT  architecture is based on the concept of die-level test wrappers, which enable testing of chips with TSVs and micro-bumps both before (“pre-bond test”), during (“mid-bond test”), and after (“post-bond test”) stacking, as well as after packaging.

"This new DfT solution is the latest example of our commitment to the emerging area of 3D-IC,” said Brion Keller, senior architect at Cadence. “Over the past two years, we’ve introduced 3D-IC TSV and silicon interposer capabilities, and, just three months ago, the industry’s first wide I/O memory controller IP solution, with a robust 3D-IC integration environment."

Cadence and Imec created the design flow automation for adding 3D-enhanced IEEE 1500-based die wrappers to existing chip designs. This was done by enhancing the existing IEEE 1500 wrapper insertion support in the Cadence Encounter RTL Compiler synthesis product. Initial results on customer designs showed that the 3D DFT structures can be implemented with negligible area costs — about 0.2%, far less than what some electronics industry watchers have speculated.

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