ARLINGTON, VA -- Jedec has approved a thermal transient testing-based measurement methodology for junction-to-case thermal resistance of power semiconductor devices.

The new methodology is said to ensure much higher accuracy and repeatability than classical steady-state measurements based on older standards. JESD51-14, standard“Transient Dual Interface Test Method for the Measurement of the Thermal Resistance Junction-to-case of Semiconductor Devices with Heat Flow through a Single Path,” describes a methodology very similar to one used to characterize thermal interface materials (TIMs).

It was qualified in a round-robin test in thermal testing laboratories of five different Jedec members actively involved in development of thermal testing standards.

The original concept for the new standard came from a 2005 paper authored by Mentor Graphics and Infineon.

The new Jedec standard has been very important for end users in many industries, such as automotive electronics, where power semiconductor devices are extensively used, Mentor said in a press release.

The thermal expert group of Infineon, led by Dirk Schweitzer and Heinz Pape, conclude the following in their most recent technical publication on transient dual interface measurement, “For the target group of power packages with a single heat-flow path, the new JEDEC standard should now provide a reliable and reproducible method to determine the Rth-JC. [junction-to-case thermal resistance] … The high reproducibility of the TDI measurement enables a fair comparison between Rth-JC values of devices from different vendors.” Infineon will present the paper in March at the IEEE SEMI-THERM Thermal Measurement, Modeling and Management Symposium.

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