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Cadence, IBM to Develop Joint DDR IP

Published: 24 May 2010
 by Staff
SAN JOSE – Cadence has joined IBM to create high-performance integration-optimized IP to help deliver leading-edge designs, while reducing the risk and time associated with integrating complex SoC designs.

As part of the agreement, the firms will develop DDR PHYs, memory controllers, and protocols such as PCIe and Ethernet under 32-nm silicon-on-insulator.

The technology will be available through the Cadence Open Integration Platform, which includes an integration design environment, integration-optimized IP and on-demand integration services.

No other terms of the agreement were disclosed.
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