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Hitachi Claims 40% Cut in Design Time

Published: 30 June 2009
 by Staff
SAN JOSE, CA and TOKYO – As part of its companywide initiative to reduce design cycle time and improve efficiency, Hitachi Ltd. has employed Cadence Design Systems’ Global Route Environment (GRE) technology for Allegro PCB design.
 
Hitachi reports the measure has reduced PCB place-and-route design time by 40% for high-speed communication products.
 
The company used the GRE technology on its PCB place-and-route from interconnect planning to complete routing, with full constraints for high-speed digital signals where automation had not been previously available.
 
Hitachi feels the technology will also be effective for other PCB design challenges, such as engineering changes and routing estimation. It plans to use GRE as a standard solution throughout the design environment.
 
GRE technology provides automaton for various stages of interconnect planning and routing where no automation has been available.
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