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New Verilog-Analog Mixed-Signal Standard Approved

Published: 20 August 2008
 by Staff
NAPA, CA—Accellera announced that its Board of Directors and Technical Committee members approved a new version of the Verilog-Analog Mixed-Signal (AMS) standard, Verilog-AMS 2.3. The new Verilog-AMS standard unifies the Verilog-AMS 2.2 specification with the IEEE Std. 1364 and the Verilog hardware description language (HDL) standard.

Verilog-AMS 2.3 allows EDA software tool developers to implement EDA tools without ambiguities in the language interpretation. This version encompasses analog and mixed-signal extensions to IEEE Std. 1364 used in digital circuit design and verification.  

The AMS standard is a result of the efforts of the Technical Committee members. To participate in the Accellera AMS Technical Committee efforts, please visit www.accellera.org/activities/verilog-ams/.

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