HyperLynx DRC performs design rule checking on printed circuit board layout databases. Driven by customizable rules, it can be executed during the PCB layout process to highlight potential high-speed design issues pertaining to signal integrity, power integrity, and electromagnetic interference. Comes with a standard set of coded rules targeted at PCB layout practices that have the potential to cause issues common in high-speed design. Standard rules are parametrically driven so users can customize them. Samples of such issues include traces crossing plane splits, reference plane changes, nets near board edges, coupling to I/O nets, long interconnects, termination checks, impedance variations, crosstalk coupling, power net width, and decoupling cap proximity. Permits rule creation using VBScript and/or Javascript. Is interfaced with all major PCB layout tools, including Mentor’s Expedition Enterprise, Board Station and PADSR, Cadence Allegro, and Zuken CR.

Mentor Graphics, www.mentor.com

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