Avoiding via failures caused by barrel plating separation.
PCB manufacturers face challenges in the precise registration of multiple layers, which is required to ensure reliable interconnects, and in integrating new technologies that enhance performance. We continuously optimize and simplify processes to improve efficiency, yield and maintain product quality. Balancing these factors is crucial for producing high-density, high-performance PCBs that meet the specific needs of various applications.
Here, we review and explain problems associated with conventional copper wrap plating requirements specified in IPC-6012B, and explore the advantages of the newly developed “Innovative Wrap” technology.
PCBs with via-in-pad designs undergo the VIPPO (via-in-pad-plated-over) process, where manufacturers fill the vias with either conductive or nonconductive epoxy material, then perform planarization and cap plating. Differences in CTE (coefficient of thermal expansion) of via fill material, copper plating and dielectric material cause these materials to expand at different rates during the thermal cycling that occurs during assembly. This differential expansion stresses the interconnect between barrel plating and surface copper, which can lead to reliability issues. As shown in Figure 1, in no-wrap plating, surface plating can separate from the hole plating during thermal cycles of the assembly process, causing via failures.
Figure 1. Thermal cycles induced separations, causing via failure.
IPC Wrap Plating Requirement
To avoid this risk, IPC updated IPC-6012B, “Qualification and Performance Specification for Rigid Printed Boards,” to include a copper wrap plating requirement. This amendment says copper plating should extend from the inside of the filled plated hole around the edge (the knee) and onto the surface of the PCB. Extending the copper plating around the hole's edge to the surface ensures a stronger and more reliable connection. In general, the thicker the copper wrap plating, the more reliable the PCB.
The via shown in Figure 2 is a filled plated hole with sufficient copper wrap plating. This, too, was thermally stressed like the failed via hole shown in Figure 1, but showed no evidence of separation between the hole plating and surface copper, which shows that copper wrap plating improves reliability.
Figure 2. No evidence of separation of hole playing and surface plating.
The IPC-6012 wrap plating requirement states that “the copper wrap plating minimum as specified in Table 3-2 shall be continuous from the filled plated hole onto the external surface of any plated structure, and extend by a minimum of 25μm [984μin] where an annular ring is required” (Figure 3).
Figure 3. Minimum wrap plating requirements.
Reduction of wrap plating by processing (sanding, etching, planarization, etc.) resulting in insufficient wrap plating is not permitted (Figure 4).
Figure 4. Reducing wrap plating below minimums through etching or like methods is not permitted.
Industry Issues
We can say that the general rule for manufacturing fine features is that thinner copper improves manufacturability. Still, the problem associated with conventional wrap plating is that it adds to the thickness of the surface copper foil, which in turn makes it difficult for fabricators to build products with high density and fine copper feature geometries.
As shown in Figure 4, starting with a base copper weight of 0.5oz., conventional wrap plating increases the surface thickness of the copper foil to 1oz. We started with 0.5oz. and finished at 1oz., which, during the etching process, demands comparatively wider trace widths and greater copper feature spacing on outer layers for better etching yield. Due to the high density of copper features in HDI designs, meeting spacing requirements is not always possible for PCB designers.
Figure 5. Final copper plating, showing etch details.
In addition, ink-filled via-in-pad holes require planarization after the filling process. This planarization, conversely, may remove the wrap-plated copper from a surface that was plated prior to ensure reliability. As a consequence, such PCBs do not qualify to IPC-6012B and are therefore rejected.
These limitations prompt PCB fabricators to develop new manufacturing techniques that make the design manufacturable as-is, while maintaining all IPC standards.
Innovative Wrap Plating Process Flow
The overall manufacturability and reliability of printed circuit boards with relatively fine features, tight geometries and the need for ink-filled holes depend on the innovative wrap plate methodology, system and apparatus utilized. The following series of figures illustrates a method called Innovative Wrap plating and the sequence of steps involved.
- PCBs after lamination of outer layers, with innerlayers selected (Figure 6).
Figure 6. Innovative wrap plating: lamination of outer layers.
- Copper voids larger than the primary drills are etched off from the top and bottom layers at all via-in-pad locations prior to drilling (Figure 7).
Figure 7. Etching of copper voids.
- Electroless copper plating is conducted, and wraps the outer surfaces of copper along with the glass areas where copper has already been etched off (Figure 8).
Figure 8. Electroless plating.
- All via-in-pad holes are drilled first (Figure 9).
Figure 9. Drilling of VIP holes.
- The process of electroless copper plating is carried out again; this adds another thin layer of copper onto the surface and inner walls of the barrel hole (Figure 10).
Figure 10. Second pass electroless plating.
- Plating resist (in blue) is applied onto the whole panel, leaving via-in-pad locations exposed. The resist opening is kept larger than the etched clearance that was specified in step 2. This provides some area of copper pad of the hole, leaving outer layers exposed to meet IPC-6012B callouts (Figure 11).
Figure 11. Plating resist application.
- The panel is carried through the electroplating process to plate copper in all holes to the desired thickness (Figure 12). During this step, the copper thickness is built up in the hole barrels only. The surface height of the outer copper layers remains unchanged, due to the plating resist (applied in blue).
Figure 12. Hole plating.
- Plating resist is removed (Figure 13).
Figure 13. Plating resist removal.
- Next, all holes are filled with conductive or nonconductive epoxy (Figure 14).
Figure 14. Epoxy via fill.
- The panel is planarized through careful sanding, which removes the thin layers of electroless plated copper from the outer surfaces of the panel, regaining the same base copper weight and height it started with (Figure 15).
Figure 15. Panel planarization.
- Cap plating and etching are the final steps. The electroplating process is carried out again to apply a plated cap on the filled via holes, followed by imaging and etching of outer layers to form a final circuitry (Figure 16).
Figure 16. Cap plating and etching.
Copper feature spacing requirements during the etching process depend largely upon the height of the finished copper. Unlike conventional wrap plating methods, which add to the thickness of outer copper layers, the novel wrap plating method helps fabricators achieve the required copper plating thickness inside barrels of VIPPO locations without increasing the thickness/height of the outer copper layers. This ensures a better etching yield. Having said this, the same base copper thickness is etched even after conducting the VIPPO process.
Akber Roy is chief executive of Rush PCB, a printed circuit design, fabrication and assembly company; This email address is being protected from spambots. You need JavaScript enabled to view it..
