A look at how array technology influences processes from board routing to drill to test.
“Miniaturization has made it possible for electronics to penetrate society more widely and deeply than ever before.”1 That sentence is as relevant today as when it was written in 1984. It embodies the core tenets of Moore’s law, and the associated manufacturing technologies that have enabled performance improvements in electronics at a predictable cadence for 55 years: 1) decreasing feature sizes, 2) increasing functionality, 3) decreasing cost. One of the most important innovations to accommodate increasing densification of chip technology has been the ball grid array, introduced in the early 1990s, which permits high pin counts per area relative to peripheral lead and no-lead packages such as QFNs and DFNs. The evolution of array packaging has moved from BGA to chip-scale package, to wafer-level CSP to flip-chips, defined by a steady march toward smaller balls and finer-pitch arrays (FIGURE 1).
*For simplicity, the term BGA will be used generically in this paper to refer to any grid array package.
Array pitch has profound implications for the printed circuit board industry, which must continually develop newer methods to route dense, high-I/O packages with increasingly finer pitch. In fact, it is arguable that the pitch of array packages has been the most important driver of most PCB technology developments, and will continue for the foreseeable future. As BGA pitch* continues to shrink to accommodate chip density, the number of PCB suppliers with the capability to fabricate PCBs to support these finer pitches decreases (FIGURE 2).
This article highlights some of the ways fine-pitch BGAs – those with pitches less than 0.4mm – affect six crucial aspects of printed circuit board fabrication: laser drill, laminate type, stackup, patterning (etch), solder mask and test (FIGURE 3). The ability and willingness of PCB suppliers to invest in the technology and equipment to support ever-finer BGA pitch designs can become a key differentiator in terms of their capability within the industry.
Laser drill. With BGA pitch of less than or equal to 0.4mm, it is generally not possible to route between pads. Therefore, via-in-pad is required to escape inner array pins to innerlayers; the finer the pitch, the smaller the pads, and therefore the smaller the required drill. A 0.3mm pitch array typically requires a 0.075mm drill size, which is often the lower limit of most conventional CO2 lasers. Below 0.3mm pitch, smaller holes are needed, which generally require UV lasers. These types of lasers are more accurate and produce cleaner holes but are slower and thus more costly (FIGURE 4).
There are reliability concerns with stacked µvias 75µm and smaller, with evidence that stacked µvias, particularly when stacked four or more high, are susceptible to pad lifting during reflow processing and suffer premature failure.2,3 FIGURE 5 illustrates a representative stacked µvia that lifted from the pad during reflow; this unit actually passed electrical test after reflow, indicating the via sat back down on the pad upon cooling. A shown in FIGURE 6, however, long-term reliability of the 75µm µvias was compromised, compared with 100µm µvias, which showed no failures during reflow or temperature cycling.
One solution when µvias 75µm and smaller are required is to stagger them wherever possible. When that is not possible, the second choice is to stack only two layers deep, as shown in FIGURE 7. Glickman, et al, have shown good reliability with 50µm stacked µvias when used with high-Tg laminate (Tg ~270oC) material in hybrid construction with standard laminate, as shown in FIGURE 8.4
Materials. Standard fiberglass weave patterns in conventional prepreg materials are characterized by tight glass fiber bundles alternating with open spaces that are filled in with resin, as illustrated in FIGURE 9. The laser ablation rate of resin is faster than that of glass. Therefore, the non-homogenous structure of standard prepreg materials can yield rough, inconsistent holes with poor size and location accuracy. These inconsistencies were especially pronounced with early generations of laser drills and had a significant impact on quality. Resin-coated copper materials, which do not use fiberglass cloth, were developed to solve this problem. RCC materials dramatically improved laser drill quality and offered ancillary benefits such as good dielectric performance. However, RCC materials are expensive, difficult to handle and have poor dimensional stability, so they are no longer common.
Alternate fiberglass materials flatten the weave pattern to provide more even distribution of glass content across the panel, thereby facilitating consistent hole shape and accuracy during laser drill, without changing the resin-glass ratio. The spread weave can also improve signal integrity for high-speed lines because the resin-glass ratio is less variable, thus providing a more consistent dielectric constant. The lower glass profile of these laser-drillable prepregs offers another important advantage for small (<75µm) µvias: layer-to-layer spacing of small holes must be reduced to maintain acceptable aspect ratios for electroplating; the thickness of the glass bundle can start to approach the layer spacing, which can lead to insufficient resin coverage above and below the glass for bonding. Lower profile glass weaves help ensure adequate resin coverage to prevent glass bundles from contacting adjacent copper.
Stackup. Because there is insufficient space to route conductors between interior pads of fine-pitch arrays, microvias must be used for routing these rows to innerlayers, as illustrated in FIGURE 12. For full arrays, this usually requires anylayer construction, in which blind microvias can be used on any layer, thereby providing full routing freedom. The larger the array, the more layers are required for routing.
This has direct implications on the stackup, not only driving layer count but also the overall thickness of the PCB. One of the critical design parameters of a microvia is the aspect ratio – calculated as hole depth divided by hole diameter – which governs the ability of the fabricator to plate the hole. Generally, the ratio must be less than 1:1, with a typical target of 0.75:1 (FIGURE 13). Thus, as ever-decreasing array pitches require smaller µvias, layer-to-layer thickness must also decrease to maintain acceptable aspect ratios.
With traditional HDI construction, the core layer is usually a C-stage (fully cured), rigid copper-clad laminate, and forms a structural backbone of the buildup, providing support during fabrication. But with anylayer technology, there is no traditional “core” layer for support, and the thin starting layers are fragile and not compatible with conventional processes (FIGURE 14). Anylayer technology, therefore, requires suppliers invest in specialized processes and equipment to fabricate coreless stackups and thin buildup layers, such as horizontal etching, vertical continuous plating, automated loading/unloading robots and other techniques to minimize processing and handling damage. It may also be necessary to process the center layer using a release backer that provides support throughout the initial processing steps and is then discarded upon the first lamination cycle.
Buildup technology used in HDI, especially anylayer construction, requires sequential processing, whereby each buildup layer must be processed through all of 10 to 15 steps sequentially. Each buildup sequence is thus nearly equivalent in terms of process time and resources as a single standard technology PCB. Fabricators that support high-volume anylayer technology require tremendous capital investment, particularly in bottleneck processes such as drilling and lamination where redundant equipment is essential to maintain volume capacity. FIGURE 15 highlights the cost implications for anylayer designs.
Patterning. Ultra-fine pitch devices, those with pitch <0.3mm, may require routing between innerlayer pads. The typical line widths necessary to route between pads of fine-pitch arrays are summarized in FIGURE 16. Conventional imaging and etching techniques are insufficient to support these requirements. Line widths below 60 to 75µm generally require laser direct imaging (LDI) because standard phototools introduce too much variation due to alignment and resolution imperfections. Conventional etching, or subtractive technology, uses liquid etchant to remove unwanted copper. This technique produces undercut, since the etchant is in contact with the top of the trace longer than the bottom. With standard line widths, undercut has a negligible effect on signal performance at normal frequencies, but with line widths ≤40µm, undercutting the normal variation of the etching process can overetch lines and even remove them entirely (Figure 16).
Additive processes must be used for ultra-fine lines. The most common type is modified semi-additive patterning (mSAP). In this process, dry film is used to mask non-pattern areas, and the desired conductor pattern is exposed to electroplating. Thus, the pattern is built up rather than etched down. Figure 13 provides a graphical comparison on typical conductor shapes using subtractive vs. additive patterning.
Solder mask. Liquid photoimagable solder mask, by far the most common solder mask process, has inherent process imaging, registration and thickness variations that can become significant when used with fine-pitch arrays. FIGURE 18 shows an example of mis-registered solder mask on a BGA array exposed an adjacent conductor. Standard solder mask registration, which uses dry film and optical exposure for patterning, is ±75µm. This is acceptable for BGAs down to 0.5mm. For finer-pitch arrays, direct imaging is required, in which light energy exposes the desired pattern, which then resists the developer material. In addition to improving the imaging accuracy compared with photo-imaged dry film, many DI processes can expose isolated regions of a working panel and make real-time adjustments to compensate for alignment inaccuracies across the panel before exposing the subsequent region, as illustrated in FIGURE 19.
Inspection and test. Finer feature sizes present various challenges for conventional inspection and test processes, including the obvious difficulty of detecting and repairing small or minor defects that would otherwise be acceptable with conventional feature sizes, but which can be significant on fine-pitch designs. Conventional PCB inspection has traditionally relied on human operators, which is time-consuming and error-prone under the best circumstances. Automatic optical inspection (AOI) has helped automate the inspection process, and greatly improved speed and accuracy. It does not replace human inspectors; instead it identifies the type and location of defects detected and sends that information to the human operator, who can then focus on the areas of concern and qualitatively judge the severity and significance of the defects.
Automated repair systems improve the speed and accuracy of the repair process and can perform more complicated repairs than human operators, as well as provide the ability to repair opens, something not normally possible by operators.
The steady advances in semiconductor technology that have enabled increased functionality in increasingly smaller packages have facilitated astonishing product advances in every sector of society but present unique challenges to the printed circuit board industry. In particular, the ever-decreasing pitch of BGA packages directly impacts most key PCB fabrication processes and requires significant capital investments. There is opportunity for suppliers willing and able to make the investments, but also risk: A recent slowdown in the smartphone market left the industry with a lot of idle mSAP capacity. If we’ve learned anything from the long journey in electronics miniaturization, it’s the PCB industry is resilient and resourceful and always seems to stay one step ahead in the inexorable drive to make things smaller.
1. W.A. Atherton, Miniaturization of Electronics. In: From Compass to Computer, 1984.
2. Bill Birch, Ivan Staznicky and Joe Smetena, “Reliability Testing of Multiple Level Microvia Structures Following Exposure to Lead-Free Assembly,” SMTA International Proceedings, September 2017.
3. J.R. Strickland and Jerry Magera, “How MSI Applied Technology Beat the Microvia Hidden Threat,” IPC High-Reliability Forum, May 2018.
4. Michael Glickman, et. al., “SLP+,” IPC Apex Expo, February 2018.