A look at how array technology influences processes from board routing to drill to test.

“Miniaturization has made it possible for electronics to penetrate society more widely and deeply than ever before.”1 That sentence is as relevant today as when it was written in 1984. It embodies the core tenets of Moore’s law, and the associated manufacturing technologies that have enabled performance improvements in electronics at a predictable cadence for 55 years: 1) decreasing feature sizes, 2) increasing functionality, 3) decreasing cost. One of the most important innovations to accommodate increasing densification of chip technology has been the ball grid array, introduced in the early 1990s, which permits high pin counts per area relative to peripheral lead and no-lead packages such as QFNs and DFNs. The evolution of array packaging has moved from BGA to chip-scale package, to wafer-level CSP to flip-chips, defined by a steady march toward smaller balls and finer-pitch arrays (FIGURE 1).

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