Could understanding the full scope of the tradeoffs unchain users from basing decisions on dielectric performance alone?
Over the past decade it has become increasingly common for PCB designers to specify a material supplier or material type based on the criteria of electrical hysteresis and other strictly electromagnetic (EM) phenomena. Designers of circuit boards for very advanced applications where EM signal losses are critical often use such materials to good effect. But the downside is that the PCB manufacturer has little flexibility in the selection of these materials, and it is becoming even more common that once a material has been used for the initial build, it is increasingly difficult to obtain approval to change from that material to a different one.
There are a couple of reasons for this trend.
First, due to the requirements of a given design, a designer will often select a material based on a material data sheet that represents the electrical characteristics of the dielectric, believing this material is the best or only option available.
Second, it is generally believed fixing (or locking in) the base material is a method by which the designer believes the critical variable known as the base material can be ensured as stable, thereby mitigating fluctuations in the finished product due to changes in material performance and selection.
While there are applications where very tight control over the selection of the material makes sense, thereby eliminating any later variation in the base material selection, this approach is simply not necessary in the majority of applications, nor will it address other underlying performance factors. As we move further from flexibility in the selection of the base material, is being locked into a single material supplier or single material type really in the best interest of the end-user? Is the presumed benefit derived from this tight control as compelling as believed?
We also need to consider whether we are properly considering the risks or downsides that accompany these limitations or controls. This narrow approach puts the focus on the theoretical, advertised electrical characteristics of the base material. Focusing on the dielectric’s electrical characteristics only under pristine circumstances, and not on other critical variables within the material and PCB manufacturing process, is an incomplete approach to design and particularly to manufacturing. This can also mean increased cost, lengthened lead times and limiting sourcing flexibility.
Consider how and why the original material selection was made in the first place, and then ask why we have developed such inflexibility when it comes to changes to the material following the initial design build.
For many standard products, the initial material selection is still left to the PCB manufacturer, but as mentioned, this is coming more under the control of the designer.
Since electrical characteristics and reliability are increasingly critical to product performance, PCB designers have become much more active from the initial build in designating said material. Now we must ask what the material selections are based on.
Some materials have gained leading positions in the market and design community because of the specific performance of the dielectric material between the copper layers. PTFE, ceramics, and special E-glass, custom resin, exotic fillers, and other components that make up the dielectric between the copper layers have shown specific measurable characteristics that may be significant in terms of achieving the product’s target performance.
Sometimes, however, these materials’ market acceptance is due to dielectric performance alone. In other cases, these materials’ reputation is enhanced or even embellished by aggressive marketing. In the case of high-speed, low loss, cellular, and RF applications, many materials are specified by brand and model or part number. And yet regardless of the purported benefits, the deficiencies of these materials, including increased manufacturing difficulty, lower yields, lack of dimensional stability, longer lead times, higher costs, etc., are not well disclosed.
The performance focus is typically the specific electrical characteristics, DF (dissipation factor or loss tangent) or Dk (dielectric constant) of the dielectric material between the copper foils.
While these dielectric materials may meet many of these performance targets, the characteristics of dielectric itself will not ensure the PCB achieves its performance target. Some of the more standard materials used in the industry may be better suited, bringing lower costs, easier manufacturability, and satisfactory performance.
We begin by looking at what is often not fully understood, and what certainly is not discussed enough between the design community and the PCB manufacturing companies: i.e., that the end target is not the performance of the dielectric; it is the performance of the PCB.
While the dielectric characteristics of PTFE and other specialty base materials appear to be excellent, other considerations must come into play; other factors aside from the chemical and molecular composition of the dielectric itself can significantly influence the performance of the PCB. These factors can improve the performance characteristics of what are considered more standard material, and in turn can be responsible for inconsistent or lower performance in the use of materials with PTFE and specialty dielectrics. The factor most often overlooked is the influence of the copper surface, i.e., the copper on either side of the dielectric – and by this we also mean both sides of the copper layer.
By definition (FIGURE 1), the bottom side is the copper surface against the C-stage (or core), and the top side is the copper surface against the B-stage and/or solder mask.
Figure 1. Dielectric (top copper; bottom copper).
The topography or structure of the dendrites on the copper (resembling “teeth,” defined below) plays a significant role in affecting the electrical characteristics of the materials, and ultimately, PCB performance. For DF, the impact from the copper structure has been shown to be 35% or more.1
When examining the topography of the copper, look first at the base foil for the dendrites or teeth of the copper foil as they penetrate into the dielectric core (material C-stage). There is a significant difference between the teeth on different types of copper foils. For example, standard ED foil is high-profile copper (referred to as THE, or shiny copper), and has larger, longer and wider teeth when compared to those on foils such as the following:
- RTF: reverse treat foil (same as drum-side treated foil, or DSTF);
- LP: low profile;
- VLP: very low profile;
- E (or) H-VPL: extra-very low profile copper foils.
What is the difference between these foils?
We can see the high-profile teeth can well exceed 0.5 mil (0.0005") in length, whereas the VLP copper has teeth a fraction of this size. The lower profile copper increases the surface area at the point of contact with the dielectric material. This improves signal integrity and reduces signal loss. It also permits more uniform etching of the copper circuit. The larger dendrites on high-profile copper cause a variation in total copper thickness and can be trapped by the dielectric, and thus not etch as uniformly as lower profile copper. The smaller teeth on lower-profile copper result in better definition of the copper circuit carrying the signal.
Figure 2. High-profile foil (at left); VLP (very low profile) foil (on right).
The bottom side, or the side against the core, is provided by the laminate supplier. Many high-performance laminates are already provided with low-profile coppers for this very reason, although lower profile copper can be requested on standard laminates. With lower-profile copper, one will most likely see measurable improvement in DF, loss, controlled-impedance tolerances and PIM counts with any base material or dielectric.
In FIGURE 3, the top side of the copper is the area where the most incremental gain from optimization within the PCB manufacturing process will be realized. As the copper circuit of an innerlayer is prepared for lamination, or the outerlayer copper of an etched circuit is prepared for solder mask, we find a wide variety of methods are used to prepare or roughen the surface. These methods range from mechanical to chemical or even a combination of both. Within each method or group we find a wide range of sub-groups. For example, in lamination preparation we see micro-etches, some aggressive, some self-limiting. We also may see oxide replacements and other coatings. All come with different rates of addition or subtraction of material, and consequently different surface topographies.
Figure 3. VLP electrodeposited copper foil.
In the past, the primary objective was to ensure adhesion of the mask, or of the multilayer lamination bond, but we must look deeper to understand the influence of these processes on the electrical performance of the PCB.
The copper structure of the top copper against the B-stage (inside the multilayer package) has the same influence as the foil topography of the copper against the C-stage. As the topography changes, so too will the DF and other electrical performance characteristics. The top copper on the surface facing out under the solder mask (or against the final finish) can also influence certain electrical characteristics.
While copper topography is one of the most impactful variables, it is not the only factor that can significantly affect electrical performance. Other contributing factors include final finish, solder mask type, application methodology, and many others. Once these variables are understood and controlled, performance and consistency will improve, even when using what are considered more standard materials.
Conclusion
Collectively, the industry has tended to look exclusively at the dielectric of the base material, but in doing so has often missed other controllable factors, such as copper layer topography, that can greatly influence the electrical performance of the PCB. Before limiting material selection to only one choice or specific types that might solve one issue only to introduce other challenges, understand these factors and how to control them. For example, proper understanding and control of the copper structure can offer great gains in performance. In many cases, control of this factor can be enough to allow the designer and fabricator to use more standard materials that are more manufacturable and in many cases cost much less.
References
1. Scott Hinaga, Marina Y. Koledintseva, Praveen K. R. Anmula and James L. Drewniak, “Effect of Conductor Surface Roughness upon Measured Loss and Extracted Values of PCB Laminate Material Dissipation Factor,” IPC Apex Expo Proceedings, March 2009.
Roy Akber is chief executive officer of Rush PCB, a printed circuit design, fabrication and assembly company (rushpcb.com); This email address is being protected from spambots. You need JavaScript enabled to view it..
