With complex board designs, constraints represent both the boundary and the finish line.
Board-level design has undergone a revolution of sorts over the last several years. While once a net was a net, now the design of the signal propagation paths has become the essence of the design. Much of the detailed logic has been consumed within the huge ASICs, FPGAs and special function ICs. But the way these ICs communicate and interact - the interconnect design - has vastly increased in complexity. High-performance designs can no longer tolerate long net delays, inconsistent bus transitions or excessive noise. The design environment common within ICs has been extended to include the board, and new tools and methodologies have emerged to give the system designer a competitive edge.
The schematic is still the fundamental tool for capturing the design concept. Schematics have evolved to fully support hierarchical abstraction, allowing complete systems to be represented with clearly understandable functional blocks. A memory interface may be represented as a block with a control, address and data bus going in, and an output data bus going out. The details of how data is provided within a few nanoseconds is hidden from view, but can be easily accessed by pushing into the block and seeing the parts that were used and how they were connected. This multi-tiered working block diagram organizes and manages the complexity of a great idea.
While the schematic is great for capturing the functional relationships, designers also need to capture the performance requirements of these relationships. An engineer would like to think of a net as an instantaneous connection, but in practice it is more like a road where signals take a finite time to propagate and their electrical behavior has to be tightly controlled. An engineer must always be thinking about how much time a signal may take, how much noise it can tolerate, and how much earlier or later it can arrive than its peers.
In order to capture these signal propagation requirements, or constraints, a new way of capturing board design information needed to be developed. Initially, constraints were added as simple attributes to the schematic nets. The complexity of the requirements soon overwhelmed this technique, and designers realized that they needed a new way of looking at their designs. A more physical view had to be provided to the engineers so that they could assign constraints to nets that span multiple hierarchical blocks, and so that physical constraints could be assigned based on the layer stackup and electrical characteristics of the PCB. The schematic needed to be supplemented with some physical data that better represented what happens when a signal leaves a part and journeys to multiple destinations.
The ideal method for displaying and editing constraints has proven to be a spreadsheet (Figure 1). A spreadsheet can easily display a list of nets as rows and constraints as columns. The intersecting cell stores the specific value of the constraint, such as the delay in nanoseconds. The physical layers are also displayed as rows in the spreadsheet, and layer-specific constraints are specified in the cells. With this type of tool and representation, the real world of propagating signals and physical board layers is made apparent to both the design engineer and layout designer, providing a common interface for specifying what has to happen to the signals and traces in a complex design.
FIGURE 1. A constraint editor provides a physical view of the design.
|
Capturing Board Characteristics
Now that the engineer and layout designer have a common tool for looking at the physical performance of a design, it is important that both have an understanding of what needs to be specified and how to do so efficiently. The first step is to capture the physical board characteristics, which are the foundation for all the signal propagation behavior. A stackup editor is used to represent the layers of the board and the dielectric constants of the material separating the layers. The resulting impedance provides the basis for the signal propagation behavior on each layer. You may recall from electromagnetic classes that a wave likes a smooth path with no impedance discontinuities, so all high-speed nets must be treated as wave guides. Any change in impedance causes some of the wave energy to reflect, changing the amplitude of the signal over time and causing noisy signals that turn ones and zeros into unpredictable values. By knowing the layer impedance, which layers are power and ground planes, and the layers that carry signals, the landscape is defined that the signals must journey through to make successful and fast connections.
In a constraint-driven design, all nets have both electrical and physical requirements, so two types of classes may be defined in the constraint editor. Net classes are used to define a set of physical requirements for a net and can be applied to all groups of nets that share the same physical requirements.
For example, a power supply net may need to have a minimum width of .010", while a clock net may have a minimum width of .005", and a net-to-via clearance of .008". All these requirements can be specified within the net class, and then applied to dozens of nets that need to adhere to these characteristics. Other physical characteristics that need to be defined include trace widths, via assignments and differential pair spacing. Clearance rules are also important for meeting manufacturing requirements. They include trace, via, pad and plane spacing, and even class-to-class clearance rules. Class-to-class clearance rules make it easier to specify unique restrictions for signal types, such as spacing between clock and power nets. All of these physical rules are passed to the router so that the traces are implemented within the constraints that have been provided.
It would be convenient if one set of physical rules were enough, but often a board is not that simple. Dense BGA packaging containing over 1,500 densely packed pins creates regions on a board that need a special set of rules. Other areas of a board may have to follow highly restrictive rules in order to implement a specific memory bus standard, such as dual data rate (DDR). For these board areas, a separate set of clearance rules and trace and via properties needs to be defined. When the board is routed, the router follows the restrictive rules when a trace enters one of the defined areas (Figure 2).
FIGURE 2. Physical rule sets define goals for router.
|
The other aspect of constraints focuses on the electrical view, or the performance of an electrical signal. Engineers have timing budgets that include the delay from the driver on one device to the receiver on another. After calculating all the intrinsic delays and factoring in the setup time, the delay on a trace can only be a limited amount of time. Sometimes the concern is not only how long the delay is but also that the delays of all the signals in a bus match within a given tolerance. It is critical to be able to capture this intellectual property in such a way that the physical implementation conforms to the design requirements. Many companies now see their constraint sets as the crown jewels of their board designs. The constraint sets determine both the performance and manufacturability of their leading-edge designs.
Electrical constraints are also conveniently grouped into classes, allowing a group of nets or a bus to all be assigned the same constraints. Electrical constraints may be described in either electrical terms such as delay, or in physical terms such as length, depending on how the designer is thinking about the problem. Other factors that affect the delay and signal quality include stub length, number of vias and topology. The topology tells the router what type of scheme to use when routing a net to multiple receivers. Some protocols require a daisy chain sequence, where each net connects in order to the next closest receiver. Others require a more balanced distribution of the signal, which can be achieved through topologies such as star or H-tree, where a centrally located virtual pin distributes the signal equally to all destinations. All of these characteristics can be applied to single nets or to busses, and then passed to layout for rules-based routing.
Some electrical constraints are driven more by signal integrity issues than propagation delay. High-speed signals running in parallel for long distances induce noise in each other, causing unintended signal transitions or unpredictable transient switching points. The constraint tool has the ability to specify the maximum parallel routing or the maximum crosstalk, as well as maximum overshoot and undershoot. This directs the routing engine to make parallelism adjustments that improve signal quality. The constraint editor should also take into account termination strategies by displaying nets as both electrical nets (including terminating networks) as well as physical net segments. Some constraints may be applied from driver to receiver including the terminating components, and some constraints may be applied only to the physical trace segment. The signal quality requirements must be captured during the design phase when the engineer is thinking about what the performance of a net has to be in order to make the design work properly.
While the routing environment tries to use constraints effectively, sometimes knowing what the constraint should be is the main problem. Questions such as "How do I know what the value of the termination network should be?" or "How do I know how much parallelism I can afford on my address bus?" arise. To solve these problems quickly and effectively, it helps to have a signal integrity analysis engine built into the constraints environment. It should be easy to specify a topology, max length and termination network and have these constraints analyzed while including the electrical characteristics from the board. An analysis engine should use the net and board characteristics to estimate the electrical behavior of the net or set of nets, analyzing delay, ringing and crosstalk. The engineer then adjusts the constraints to optimize performance without overly restricting the router. Varying the parameters over specified ranges gives the engineer a set of allowable constraints that meet the design requirements.
Just as schematics use hierarchy to abstract a circuit's function, a constraint editor uses hierarchy to abstract constraint classes. Suppose a reduced latency DRAM circuit (RLDRAM) is being designed. A top-level class called RLDRAM that captures the general requirements for the design may be created as well as specifying sub-classes that define special requirements for the address bus, the data bus and the clocks. Further subclasses of the data bus might also be defined, isolating unique characteristics of different data lanes. By using hierarchical constraint techniques, it becomes easier to group and apply the carefully specified requirements for a type of design (Figure 1).
Constraint Reuse
Many board designers now claim that they spend more time on the constraint definition than they do on the schematic design. If this is true, then how can the designer's productivity be improved? Again, a concept that was developed for schematics - design reuse - is called upon (Figure 3). Constraint reuse has the potential to do for board design what design reuse has done for logic design. It can greatly reduce development time and greatly improve the design quality by reusing proven constraints that have led to routed board designs that function reliably in production. Constraint templates capture the topology and connections of a type of net into a transportable, generalized format. The template specifies that a driver from a type of part is connected to a set of receivers of other types of parts, but it does not say which reference designators to use - any part type match will do. So, if a DDR design has been done before and a template of the constraints used has been saved, the template can be applied to a new schematic that uses the same types of parts. It is OK if the connections don't match exactly; the portions of the template that apply are used. This saves a great deal of time in implementing common standards on new designs.
FIGURE 3. Constraint templates enable reuse, saving you time and hassles later.
|
High-speed, complex board designs are pushing the performance envelope. Propagation delays and signal quality issues have expanded from the IC to the board, where the concern is for the optimal performance of the entire system. A few nanoseconds do make a difference, and high performance routers are now capable of honoring design constraints that get the most performance out of every trace. Constraints represent both the boundaries and the finish line in the race to get the most optimal design possible to market before the competition does the same. PCD&M
Bruce Caryl is business development manager at Mentor Graphics; This email address is being protected from spambots. You need JavaScript enabled to view it.. John Dube is technical marketing manager at Mentor Graphics; This email address is being protected from spambots. You need JavaScript enabled to view it..
