Your board is almost routed. You were careful to get all the important fast traces on dual stripline. You had to cut the design rules really close, but you think everything will be OK. Instead of keeping the spacing between lines on the same layer at least three times the line width, you're down to twice the line width in some cases.
But you still have one line to route. If you can fit it in the board, you can keep the layer count to 10 layers. Otherwise, you have to pop it up to 12 layers and spend another three days re-routing everything. Try as you might, you can't get this last line routed within the current design rules. But you found a sneak path that looks like it might work, and it's still on grid.
The only way you can fit this line in the current board stackup is if you route it parallel to the signal line in the adjacent signal layer above. This violates the rule that you should only use orthogonal routing layers that share the same reference planes in dual stripline. But, it's only for an inch. This should be short enough, right? Nobody will notice, will they? And the board can be done in two minutes, out to fab in five and back from stuffing in three days so you'll meet the unrealistic schedule.
It's only an inch. But in that inch, the two single-ended transmission lines are routed, not as dual stripline, but as broadside coupled lines, as shown in Figure 1.
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This geometry should be avoided because of the large amount of crosstalk between the two signal lines. In a typical stackup with .006" wide lines, and each of the three dielectric layers is .005" thick, the saturated near-end crosstalk coefficient (NEXT) in broadside coupling is about 15%. Keep in mind that the typical noise budget for crosstalk is about 5%. With a 3.3 V signal, the noise budge for crosstalk is typically 150 mV.
You would need to increase the separation between the two signal layers in the dual stripline to more than 3x the thickness of the signal to the adjacent return plane to reduce this broadside coupled noise to 5%.
But there is hope in this design. If the coupled length over which the two lines are co-parallel can be kept short enough, well below the saturation length, the near-end noise can be kept below 5%.
Here's a simple rule of thumb to estimate the near-end noise. The near-end noise, Noise% = NEXT x (coupled length)/(saturation length), with
Noise% as the percent of the near-end noise to the signal voltage
NEXT = the saturated near-end crosstalk coefficient
Coupled length = co-parallel run length (Len), in inches
Saturation length = 0.5 x rise time of the signal (RT) x speed of signal (v), in inches
For this dual stripline geometry, the rule of thumb boils down to
Noise% = 15%/3 x Len/RT = 5% x Len/RT, with Len in inches and the rise time in nsec.
As a rough rule of thumb, if you want to run two lines co-parallel on adjacent layers, you better keep the co-parallel length, in inches, shorter than the rise time, in nsec. If the rise time is 1 nsec, you can probably get away with 1" co-parallel run lengths.
Figure 2 shows the simulated noise voltage on the quiet line when a 3.3 V signal with a 1 nsec rise time passes through a region where the quiet line runs co-parallel underneath the active line.
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When the rise time is 1 nsec, the length of the rise time is 6 inches and the saturation length is 3". To reduce the near-end coupled noise to 5% when the NEXT is 15%, we need to keep the coupled length below one third of the saturation length, or 1".
This simulation confirms that when the coupled length is 1", the near-end noise is about 170 mV, close to the allowed budget. In this case, you can probably get away with the 1" overlap. If the rise time were 0.5 nsec, the 300 mV of near-end noise might cause you to have to re-spin the board.
Now look what happened to your schedule. PCD&M
Dr. Eric Bogatin is president of Bogatin Enterprises. He is the author of Signal Integrity - Simplified, published by Prentice Hall; This email address is being protected from spambots. You need JavaScript enabled to view it..