Timing concepts for digital design margin optimization and failure prevention.

In high-speed design, the need frequently arises for board-level (static) timing computations, in order to maximize system performance (margins) and to avoid failures. Signal integrity analyses often involve evaluation of both signal quality and timing margins. However, signal quality degradations - such as overshoot, ringback, etc. - can be tolerated in many cases provided they do not adversely affect timing. As an example, for PCI/PCIX bus a large amount of ringing is acceptable if it does not cause timing violations.

This three-part series will address numerous high-speed timing concepts. Part 1 will discuss timing diagrams and parameters.

Timing diagrams (voltage vs. time) are graphical representation of circuit behavior over time, and can aid system analyses.

Figure 1 diagrams two signal types commonly encountered in digital timing analyses.

Figure 1a illustrates pulse-possessing width (Pw), rise time (Tr), fall time (Tf), Period T, low voltage (Lo) and high voltage (Hi). The signal initiates Lo to Hi transitions at times t1 and t3, and Hi to Lo at t2. For a pulse train, T is reciprocal of frequency F and its duty cycle (defined as time fraction occupied by the pulse¹ equals the product of frequency and pulse width. Here, the rise/fall times are defined as times from points 0% to 100%. However, Tr and Tf may be also measured² at 10% to 90%, or 20% to 80% points. Figure 1b shows a data pulse of duration Tw with state transitions occurring at the crossing points (i.e., t1 and t2), which may be Lo to Hi or vice versa.

Figure 2 is a functional timing diagram demonstrating causal relations (by curved lines) leading from input to resultant output transitions. This figure shows switching as instantaneous (vertical lines), although in reality non-zero times are required for such transitions.

Timing analyses of a high-speed net usually necessitates taking into consideration driver and receiver chips timing specifications. These IC specs are of two types: timing requirements and guaranteed responses. Among timing requirements (constraints) are setup time, hold time and pulse width. A typical guaranteed response is a chip's propagation delay. Constraints normally have either a maximum or minimum (but not both) unlike delays, which almost always contain both minimum and maximum values.

Several timing relationships are displayed by Figure 3. In the shaded regions of Figure 3a data can change, but within the remaining interval it must maintain stability. The data setup (Ts) and hold (Th) times are also defined. Figure 3b depicts in-out signals plus associated propagation delay (maximum delay between input and output signal changes) timing specification.

Timing parameters and reference test loads are normally obtainable from AC (dynamic) specifications of device's datasheet³, as exemplified by Figure 4.

Depicted by Figure 4a is an AC timing table for an Infineon Technologies DDR SDRAM⁴. Figure 4b shows the AC output load circuit diagram (timing test load) for that chip.

Among important timing parameters are clock to out Tco (equals time from clock rise³ to measurement voltage Vmeas into test load), set-up/hold requirements and jitter.

In order to calculate timing budgets, it is frequently necessary to determine propagation time via simulation as demonstrated by Figure 5. A free version of Cadence Design System's PSpice was utilized for this simulation.

A value for C_load was ascertained assuming that receiver is an Infineon Technologies DDR SDRAM (32Mbx4), part number HYB25D128400C[C/E/T] in a 66-pin P-TSOPII (plastic thin small outline package Type II). Its associated IBIS model (128m_d11.ibs) indicates typical C_pkg = 0.434 pF, and nominal C_comp = 4.1 pF (for IO_FULL buffer). Subsequently, C_load, which is the sum⁵ of C_pkg and C_comp is typically 4.534 pF as used in this simulation.

The driver U1 is a pulse of 2.5 V amplitude, having parameters (as defined by Figure 1a) of Tr = Tf = 0.5 ns, Pw = 4.5 ns, and T= 10 ns. They are related via:

Pw = (T/2) - (Tr + Tf)/2

Figure 5b shows the waveform results at driver (in red) and receiver (blue). The rising edge propagation delay is measured from midpoint of a driver rising step (t = 10.24 ns, v = 0.8 V) to midpoint of corresponding receiver rising step (t = 11.12 ns, v = 1.25 V) as indicated by green marker line yielding a delay of ~ 0.88 nsec. Similarly, the falling edge propagation delay obtained from midpoint of driver falling edge (15.25 nsec, 1.7V) to midpoint of receiver falling edge (16.12 nsec, 1.25 V) is ~ 0.87 nsec.

This delay exceeds the line's TD of 0.7 nsec because of the loading effects of receiver U2. It is interesting to note that at v = 0 V there is negligible effect from receiver loading and the delay between driver and receiver is ~ 0.7 nsec. However, when signal transitions occur the receiver loading effects on delay become evident, as indicated by ~ 0 .88 nsec.

Stay tuned for Part 2.   PCD&M

Abe (Abbas) Riazi is a senior staff electronic design scientist with ServerWorks (a Broadcom Company) in Santa Clara, CA; This email address is being protected from spambots. You need JavaScript enabled to view it..

ACKNOWLEDGEMENTS

My gratitude to Clement Yuen, Peter Arnold, Jeremy Plunkett and Dean Gonzales of SeverWorks and Oliver Kiehl of Infineon Technologies.

REFERENCES

1. 1. J.A. Coekin, "High-Speed Pulse Techniques," Pergamon Press, 1975, P. 3.
2. 2. William R. Blood, Jr., "MECL System Design Handbook," 4th edition, Motorola Inc., 1988, P. 19.
3. 3. Todd Westerhoff, "Closing the Loop Between Timing Analysis and Signal Integrity," Cadence Online Seminar, August 28, 2000.
4. 4. Infineon Technologies HYB25D128 [400/800/160]C[C/E/T] (L), 128-Mbit Double-Data-Rate SDRAM, Data Sheet, Rev. 1.4, Nov. 2005, P. 18, P. 68, P. 73, P. 94.
5. 5. Abe Riazi, "Stub or No Stub?," Printed Circuit Design and Manufacture, October 2004, P. 18.

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