Schematicless approach makes inroads. But don't write off schematics just yet.
Network routers, 3G cell phones, high-definition TVs, military display systems, aerospace electronics, and other high-end computer products all have one thing in common - printed circuit board systems replete with high pin-count devices. Based on the extraordinary performance of these products, this is not a surprising fact, but it is one that has far-reaching consequences in terms of PCB design, especially schematic design capture.
To understand why, we don't have to look very far into the past. Designs that only recently consisted of a variety of small and medium pin-count devices and an occasional large FPGA or ASIC have given way to designs with a relatively low number of active components - primarily high-performance, high pin-count integrated circuits and FPGAs. In general, high pin-counts mean increased interconnect complexity. To a front-end designer, it can mean designs that run to hundreds of schematic pages and an exceptional number of design problems.
As is often true in times of change, there is an opportunity for designers and software tool producers alike to look at traditional processes and consider how to improve them. In the case of design capture, productivity and performance advancements will require a new approach - one that enables schematicless design.
But realize first that designers have ample reason to be concerned about the challenges of capturing large pin-count devices using existing schematic-based technology. Due to the complexity of these designs, it is no longer possible to create a schematic that is a visual blueprint of a design. High pin-count devices require symbols to be broken up over multiple schematic pages, causing a large increase in the number of pages. Without a doubt, a design spread over 100 schematic pages has lost any pictorial advantage. Simply managing that much data puts its integrity at risk; there are too many opportunities for error. Additionally, large symbols leave little room for logical wiring forcing all connections to be formed via signal names, a time-consuming process at best.
A schematicless approach can help overcome these obstacles and provide substantial benefits. In overview, the methodology is enabled by a spreadsheet or high-level design language (HDL) that is used to represent the connectivity of a design. After components are added to the design and connections assigned, a netlist is generated, and the data is sent directly to the place-and-route design tool, thus eliminating the need for graphical schematic representation.
To be effective, the methodology has to be supported by design tools that allow users to quickly and easily manage the dozens of decoupling capacitors and hundreds of terminations associated with each large pin-count ICs. If the capability is fully integrated with the PCB layout system, constraint management system, and signal integrity tool, the results are shorter design cycles, increased designer productivity, improved product performance and reduced library costs.
So, does all this mean that schematic-based design is truly obsolete? For highly constrained motherboards, backplanes and other complex designs the answer is yes. Early adopters are already turning to schematicless design for their high-performance products, seeking the attendant benefits. Sooner or later all of the players in these markets will have to make the change or fall behind. But for a number of other design types - analog, power supply, and RF designs among them - schematic-based design remains a viable solution. Importantly, it allows IP from existing schematic designs to be reused.
For these reasons, new tools that support schematicless design must also continue to support schematic-driven design, allowing integration with existing schematic blocks or the creation of new schematic blocks for those portions of the design best suited to schematics. By having tools that enable both design types in a single environment, users can choose the approach appropriate to a design, in consideration of time, cost, competitive, and performance goals.
The future of design capture, in fact, lies with this multistyle design creation approach. PCD&M
A.J. Incorvaia is vice president, research and development, at Cadence Design Systems Inc.
