Could nano PCB miniaturization allow the IC world to finally merge with SMT?
I first started working in the wonderful world of high-tech manufacturing (which I now refer to as a disease) in wire and die bonding for the smartcard industry of the early 90s. I left that fledgling industry in the late 90s for the then-more mainstream SMT industry, and wound up at a Flextronics Product Introduction Center in Texas supporting PCB layout, R&D prototyping and pre-production for SMT products that would be going into mass production factories all over the world.
I've noticed over the years that the semiconductor industry and the SMT industry are desperately swimming towards each other. Recently I have seen a number of articles suggesting that there is a strong need for new materials that will further this merging of the laminate substrate and PCB industries. With the pitch of semiconductor die constantly shrinking, there is a need to reduce the pitches available on the laminate substrate, and this, in turn, will pressure the PCB industry to make finer geometries available at the PCB level.
Denser and Faster
With the ever-accelerating reduction in geometries and increasing speeds at the wafer level, manufacturers of laminate substrates are being asked to provide packages that are capable of delivering performance values that are approaching the point where they will exceed the capabilities of current materials and production techniques for cost-effective packaging. The next generation of materials and packages will need to provide better electrical characteristics, such as lower Er (Dk), lower loss tangents (Df) and the ability to work in higher-temperature environments. These materials would also need to lend themselves well to production techniques that would allow for feature sizes to down to 10 microns and below, and dielectric thicknesses of 25 microns and below.
In addition to the ability to provide these characteristics, these materials must also be cost-effective to produce, and utilize lower-cost processing for laminate substrate production than the current high-density solutions.
As an added feature, as long as we are daydreaming, these materials and the subsequent production processes would need to be such that the entry barriers to production of laminate substrates could be reduced to the point that smaller manufacturers would be capable of producing high-quality laminate substrates, in low volume, in very short lead times. In such a scenario, design and prototype cycle times could be reduced to something close to that for prototype PCBs today.
The technologies in use today that can produce such fine features as 20 micron pitch are true additive processes; many of the manufactures of these types of products apply proprietary dielectrics in order to achieve these geometries. These are very expensive processes and yield very expensive product due to both cost of processing and overly large yield losses.
One possible methodology for meeting the requirements outlined above is to provide materials with these electrical and physical properties in a laminate form, with a copper layer attached to one side, much as the currently available PCB laminate material resin-coated copper (RCC) does. However, this material would be attached to a copper layer that would be much thinner than anything currently available, and still possess adhesive forces great enough to withstand the environments that such materials would see during fabrication, assembly and life as a final product. This thin copper layer would be necessary to overcome the limitations of the subtractive processes currently in use with standard copper thickness materials.
Additive vs. Subtractive
With the subtractive processes in use today the features that are defined and plated exhibit very large differences in cross-sectional width from the top of the plated feature to the bottom, in some cases in excess of 20% of the feature width. This is due to the etch characteristics of the processes used to remove the base copper foil in those areas where there is to be no circuitry in the final product. The etching solutions utilized for this process cannot discriminate between the base foil that is to be removed and the features that are to remain, so we end up with features that possess a trapezoidal cross section, much like those in Figure 1.
FIGURE 1. Results of etching process.
FIGURE 2. Results of etching process with thin base copper layer.
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These types of materials would allow for a largely additive process, with minimal subtractive processing. The reason that these materials would exhibit straighter side walls, with much the same cross-sectional width from top to bottom, is that the etch process would be short enough, due to the very thin copper base, so that the etching solution would spend very little time attaching to the side walls of the plated features (Figure 2).
Using these materials and a process such as this, the sidewalls of these features would be approximately the same size as the image that was projected, with minimal etch factor. Such materials could possibly be utilized by current PCB manufacturers to produce geometries at the levels required without the need to spend many millions of dollars on additional - and very expensive - equipment.
With such materials, traditional lamination techniques could be utilized, along with traditional and laser drilling equipment. Imaging techniques would need to be modified to allow for the resolution of very fine lines and spaces, such as 10 microns. However, equipment manufactured today that can produce these geometries could be modified for just such a use, and purchased at a cost far less than that of current production line equipment for additive processes. Plating techniques would only need to be modified slightly, and etching costs would be minimal where small amounts of base copper would need to be removed.
In such a scenario, the circuit features produced could much more closely approach the size of the imaged feature, as the process would be largely additive. These features would exhibit little of the side wall etch associated with today's subtractive processes, due to the minimal amount of starting foil that would need to be etched off. This would allow for much better control of line widths, allowing for better predictions of product performance during design and modeling.
An additional benefit of these materials is a resistance to cathodic anodic filament (CAF) growth. This typically occurs where holes are placed very close to each other, usually 300 microns or less, and where copper migrates along the glass reinforcement fibers between these two holes, causing a short. This is typically not an issue with additive materials in that there is no glass reinforcement, and hence no pathway down which the copper can migrate. These new materials would therefore not need to possess glass reinforcement down which the copper could migrate in order to decrease geometries even further.
These materials should also possess the ability to control dielectric thickness tolerances very tightly. This would be necessary to allow designers to have confidence in the ability of manufacturers to produce product that would closely resemble the modeling done during the design phase, with minimal variance. This, again, coupled with the CAF considerations expressed above, suggests materials that have no glass reinforcement, as this introduces more tolerance into the dielectric thickness equation.
Should such materials be developed, one would assume that the manufacturers of these materials would be able to vary the dielectric thicknesses so that designers would be able to develop substrates using these different dielectric thicknesses to tune for their specific product need. If this is correct, it follows that the materials manufacturers would be able to develop these same materials in thicknesses that could address the needs of the PCB industry as well. This would mean that the PCB industry would have materials, and processes, available to them to produce cost-effective feature pitches well below those that are currently available, allowing further miniaturization of the semiconductor package.
The side benefit to this scenario would be that the semiconductor package and the PCB would be made of materials that would possess the same electrical and physical attributes, making for a very robust union between the two through the assembly process, and on into finished product life.
What Now?
New materials are needed that have no glass reinforcement, very thin copper with high adhesive forces, thin dielectric thicknesses, excellent thickness tolerances, higher Tg, lower Dk and Df, and that can be produced and processed efficiently, with lower cost processes, than what is currently available at these feature pitches. This would allow for far denser, higher speed packages that have better assembly yields that would thrive in harsher environments, than anything currently available.
If materials manufacturers get in the game, we might finally reach the level of PCB miniaturization that allows the IC world to merge with the SMT world. PCD&M
Michael Shores is president of Texas Prototypes (TXP) based in Richardson, TX. He can be reached at This email address is being protected from spambots. You need JavaScript enabled to view it..
