Symmetry, minimized impedance discontinuities and balanced loading are preferred features.

One phase of high-speed system design involves exploring a layout solution space to ascertain workable technologies and interconnect architectures for various signal groups.^1,2 Some commonly employed topologies for reliable bus design include point-to-point, daisy chain, star topology and T topology.

Several configurations are illustrated by Figure 1. Two important topology design considerations are maintaining symmetry and minimizing impedance discontinuities at each junction.² For topologies with few impedance discontinuities, it is possible to solve multiple reflection effects by applying the lattice (bounce) diagram for linear systems or the Bergeron diagram for non-linear systems.² However, for more complex net topologies it is preferable to utilize a simulator program such as SPICE for waveform analyses.

In Figure 1, each layout scheme is drawn as unidirectional, although they can be applied in bidirectional designs as well. Furthermore, no terminators are shown but termination may be required (depending on such factors as signal edge rates, trace lengths, etc.) for successful implementation. A point-to-point connection between two components produces optimum signal quality.³ However, in a majority of cases the nets are multidrop, i.e., several components are connected within a single net.

The daisy chain contains a multidrop net structure connecting three or more pins.^2,3 The route and stub lengths should be maintained as short as possible. Daisy chains function well when the net delay is short compared to rise time – the net can then be modeled as a capacitive load and the driver scaled accordingly.

Daisy chain is a frequent topology for multidrop buses, including front side bus and memory buses on personal computers.² An important disadvantage is the need for stubs to connect the middle agent to the main bus trunk. Even for very short stubs, the middle agents' input capacitance can load the bus and lower the line's effective characteristic impedance.²

Star topologies are inherently unstable and it is critical that the electrical delay and loading of each leg are identical. Otherwise signal quality can rapidly degrade. For T topologies², unidirectionality and symmetry are crucial, and sometimes the T legs are designed with twice the impedance of the base, minimizing impedance discontinuities.

Radial loading occurs when multiple traces diverge from a common point on a transmission line.⁴ Each radial line can be separately treated as distributed, lumped or unloaded depending on its loading features.⁵

Radial lines affect the transmission lines' propagation characteristic by creating the impedance Zrad (at junction point):
Zrad = Zo/N
N = Number of radial lines.

For instance, in Figure 1d, the impedance at point X where four traces diverge to the receivers is Zo/4, with Zo representing the impedance of each branch (i.e., T1, T2, T3 and T4). Or consider a differential trace with a main line and a junction from which three line pairs (with impedance of 100 Ω) diverge to differential receivers. At the junction point, the effective impedance is then 100/3 = 33.333 Ω.

The tree architecture depicted by Figure 2 is an interesting topology commonly employed for clock signals. For such tree topology, some requirements for minimizing skew include placing the clock inputs close to each other, driving them with same source and balancing the tree topology with identical – and equal numbers of – receivers (gates).⁶

It can also prove advantageous to utilize low-impedance transmission lines to reduce the sensitivity of driver chip to capacitance of receiver loads. Furthermore, as illustrated by the following example, dummy loads can be employed in some cases towards achieving optimum timing.

Due to effects of loading on signal delays or velocity, sometimes dummy loads are incorporated in a net for timing balance. Figure 3 depicts the differential clock net of an unbuffered DIMM. The DIMM layout is governed by JEDEC standards.⁷ The input section attaches to a connector, and the output portion contains differential loads (DDR SDRAMs). This illustrates output branches that are fully loaded with SDRAMs; however, it is possible for one or more of these branches to lack ICs.

The pin assignments of the 184-pin DDR1 DIMM connector J1 includes three pairs of differential clock inputs, often named (CK0, /CK0), (CK1, /CK1), (CK2, /CK2).⁷

Each clock tree contains six differential output lines for possible connection to SDRAM pins. It is then possible for a DIMM to possess a maximum of 18, or a minimum of four SDRAMs.

In a DIMM with fewer than the maximum 18 SDRAMs, the implication is that some of the clock outputs are without IC loads. It is then recommended to insert capacitors in unloaded branches to minimize delay skews for various clock loading conditions (Figure 4). The capacitance Ceff for C1, C2, C3, C4, C5 and C6 should equal one-half Cin where Cin represents DDR SDRAM input capacitance. The reason for Ceff = 0.5 * Cin (as opposed to equalling Cin) is that each differential receiver connects to a positive and a negative line.

Figure 5 illustrates how two capacitive loads (CL+ and CL-) of the same capacitance (Cin), with currents (I+ and I-) of identical magnitude but opposite directions, yield an equivalent series circuit of effective capacitance (Ceff = 0.5 * Cin). For special cases when there is no common-mode current, the common/connection point in Figure 5b represents virtual ground (a node at zero volts but not directly grounded). PCD&M

Abe (Abbas) Riazi is a senior signal integrity engineer with ServerWorks (a Broadcom company) in Santa Clara, CA. He can be reached at This email address is being protected from spambots. You need JavaScript enabled to view it..

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