Printed Circuit Design & Fab Online Magazine - Design News

Design News

CHICAGO– Electronic Interconnect Technology (EI) has added a full range of printed circuit fabrication data verification services to its menu.

Data verification allows users to sort out PCB design and DFM issues early in the design process to avoid production problems later.

“We run extensive DRC/DFM analysis on all incoming Gerber files, prototypes or production so that any issues or concerns that we find are quickly relayed to our customers,” explained Pratish Patel, president and CEO.

MAYNARD, MA – A paper written by Signal Integrity Software Inc. (SiSoft) and co-authored with Cisco Systems has been nominated as a Best Paper Finalist at DesignCon 2009.

“A Simple Via Experiment” presents an analytical model for understanding and predicting behavior of via structures, correlated to lab measurements. Theoretical, 3D field solver and measured data will be presented for an experimental via structure designed so that the experiment can be easily repeated.

Dr. Michael Steinberger of SiSoft will present the paper on February 3.

MUNICH, GERMANY and WESTFORD, MA – Zuken is offering a free download of CADSTAR 11 Schematic Design Tool until March 31.

As designs become more complex, the need for data transfer and communication between members of a design team is crucial. By providing a single design tool environment, Zuken anticipates users will be able to process designs quickly and at lower costs.

The software can be downloaded at www.zuken.com/CADSTAR, users will need to provide a MAC address to obtain a license.

ATLANTA – Intercept Technologies Inc. announced that National Instruments has chosen the Pantheon and Mozaix RF design tools for its latest generation of RF instruments.

Read more: National Instruments Selects Intercept Technology's Software Suite

MUNICH, GERMANY and WESTFORD, MA – EID has adopted the CR-5000 design platform by Zuken. EID will use the technology for its complete front to back-end methodology, including signal integrity simulation.

EID believes CR-5000 will decrease verification run time and increase layout efficiency on complex development. “Without this kind of unified design and analysis environment we would never have achieved the fast development cycle-time needed for our most demanding projects,” said JosÃ© Taborda, head of CAD department at EID.

SOUTH PLAINFIELD, NJ – Sharon Trueman has joined the design management team at R&D Circuits. As the senior applications engineer, she will be responsible for customer applications assistance and process development.

Trueman brings over 20 years of experience in the semiconductor manufacturing and test environments. For the last 8 years, she has focused on ATE load board and probe card design, holding key positions with several ATE design companies. She will be based at the Design Center located in Meza, AZ.