SAN JOSE, CA – The 14th annual International Wafer-Level Packaging Conference will be held Oct. 24-26 here.

Technical sessions are organized in these tracks: Wafer-Level Packaging, 3D Packaging, and Advanced Manufacturing and Test. The WLP track features sessions on materials, processes, design, and new technology like fan-out WLP. The 3D Packaging track features sessions on heterogeneous integration enablement, materials and equipment, processing technologies, and smart system integration and applications. The Advanced Manufacturing and Test track features sessions on test, productivity, inspection, and metrology.

UCLA’s Subramanian Iyer, Ph.D., distinguished chancellor's professor, electrical engineering, is scheduled to keynote on Packaging without the Package: A More Holistic Moore's Law.

VP Richard (Kwang Wook) Bae, corporate strategy and planning, Samsung Electro-Mechanics, will present a keynote on Samsung's FOPLP: Beyond Moore.

CEO Han Byung Joon, Ph.D. of STATS ChipPAC is scheduled to present Innovative Packaging Technologies Usher in a New Era for Integration Solutions.

Packaging technology experts John Lau, Ph.D., ASM Pacific Technology; John Hunt, ASE (US); Fernando Roa, Ph.D., Amkor Technology; and Rao Tummala, Ph.D., Georgia Institute of Technology, are scheduled to lead half-day workshops.

For more information and to register, visit  

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