SAN JOSE, CA -- Cadence Design Systems, Inc. introduces a scalable co-design solution for designing FPGAs onto PCB systems. The FPGA Planner System (for OrCAD and Allegro) was developed by Taray Inc. and is available to Cadence customers through an exclusive OEM licensing agreement.

According to Cadence, the FPGA System Planner shortens the time it takes to integrate FPGAs on a PCB, enhances FPGA performance through the optimal utilization of FPGA resources and can reduce PCB manufacturing costs through a reduction in the number of PCB layers required to route dense, complex, large pin-count FPGAs.

“I tried other tools that promised to simplify the FPGA I/O complexity issue but none of these had an approach like Taray does,” said Roberto Cordero, GCSD Signal Integrity TMT Lead of Harris Corporation. “Taray's FPGA I/O synthesis technology is the only one that allows us to enter our design intent at the system level, and then it completely automates the pin assignment over multiple FPGAs all at once.”

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