New Products
SOUTHPOINTE, PA – Fluent Inc., a wholly owned subsidiary of Ansys Inc., has announced the release of Fluent Connection 1.1 software that helps streamline the process of creating simulation models based on design data from leading CAD packages.
The Fluent UGS NX Connection, Fluent Pro/ENGINEER Wildfire Connection and Fluent SolidWorks Connection products operate within the CAD system user environments and provide tools for checking and conditioning the 3D geometry model in order to ensure that it has been properly prepared for the next step in the simulation process.
Fluent Connection is said to take into account the unique requirement of fluid flow simulations to include a description of the fluid volume inside or surrounding the 3D solid model. By helping the CAD user to identify and isolate this fluid region, Fluent Connection reportedly eliminates the need for the engineering analyst to perform this task outside of the CAD system, saving time and effort during the simulation process.
The Fluent Connection software products have been built using development tools provided under the PTC Partner Advantage Program and UGS and SolidWorks partnership programs.
"We are very appreciative of the support from our CAD/PLM partners under their software developer partnership programs," notes Ferit Boysan, vice president at ANSYS, Inc. "As a leading, independent provider of computer-aided engineering software, ANSYS understands that our customer base needs outstanding connectivity to multiple design tools and PLM systems. The Fluent Connection products are part of our strategy to help customers achieve a streamlined process that facilitates simulation-based design."
TEMECULA, CA – CWAV recently launched its newest software product, the streaming Data Extractor software. Used with CWAV's USBee AX-Pro, it provides a detailed view into embedded communication busses.
"Typically, the challenge faced by engineers is getting data out of an embedded system quickly so as to be able to process it, either to capture a bug in progress or to evaluate
performance," says Tim Harvey, principal of CWAV. "We developed the Data Extractor to address this by supporting many of the most common embedded busses available today. No other product on the market allows engineers, students and technicians to capture, find, and debug a sequence that happens hours or even days after the start of a test."
An optional software product, the Data Extractor allows for the extraction of raw data from various embedded busses to store off to disk or stream to another application. It is able to collect raw data from Parallel, Serial, SPI, I2C, I2S, High-Speed Async, USB full- and low-speed, SMBus, 1-Wire and CAN busses.
While there are other stand alone devices on the market, the Data Extractor is reportedly able to support all of the various busses, pull out transaction data on the fly, run indefinitely, capture entire test sequences, monitor embedded system data flows during normal operation, and process or store megabytes, gigabytes or terabytes of information.
"Typically, the challenge faced by engineers is getting data out of an embedded system quickly so as to be able to process it, either to capture a bug in progress or to evaluate
performance," says Tim Harvey, principal of CWAV. "We developed the Data Extractor to address this by supporting many of the most common embedded busses available today. No other product on the market allows engineers, students and technicians to capture, find, and debug a sequence that happens hours or even days after the start of a test."
An optional software product, the Data Extractor allows for the extraction of raw data from various embedded busses to store off to disk or stream to another application. It is able to collect raw data from Parallel, Serial, SPI, I2C, I2S, High-Speed Async, USB full- and low-speed, SMBus, 1-Wire and CAN busses.
While there are other stand alone devices on the market, the Data Extractor is reportedly able to support all of the various busses, pull out transaction data on the fly, run indefinitely, capture entire test sequences, monitor embedded system data flows during normal operation, and process or store megabytes, gigabytes or terabytes of information.
SAN JOSE – Cadence Design Systems Inc. has introduced Cadence Incisive Design Team Xtreme III systems, the next generation of the Incisive Xtreme series of accelerator/emulators within the Incisive functional verification platform.
Xtreme III systems are said to simplify the movement to and from simulation and acceleration engines, integrate verification management and debug environments, and support advanced verification methodologies such as assertion-based and transaction-based acceleration. As the highest density (volume per gates) acceleration/emulation system, it offers twice the performance of Xtreme Server with 10-100,000 times the simulation performance gain, supporting up to 72M gates in a single chassis.
The simulation-like, event-driven environment of Xtreme III reportedly provides several verification process automation capabilities for design teams. These capabilities include integration with Incisive Design Team Manager for plan- and metric-driven closure management, integration with the Incisive SimVision simulation debug environment, and support of SystemVerilog Assertions and SystemVerilog Direct Programming Interface.
"The proliferation of system-on-chips and the explosion of verification complexity have resulted in a thirst for more performance at the designer's desktop," said Steve Glaser, corporate vice president of marketing, Verification Division, Cadence. "The Xtreme III series was developed specifically to deliver acceleration to a broad set of design engineers by making it easy for them to use the advanced verification methodologies required to reach predictable verification closure."
Xtreme III systems are said to simplify the movement to and from simulation and acceleration engines, integrate verification management and debug environments, and support advanced verification methodologies such as assertion-based and transaction-based acceleration. As the highest density (volume per gates) acceleration/emulation system, it offers twice the performance of Xtreme Server with 10-100,000 times the simulation performance gain, supporting up to 72M gates in a single chassis.
The simulation-like, event-driven environment of Xtreme III reportedly provides several verification process automation capabilities for design teams. These capabilities include integration with Incisive Design Team Manager for plan- and metric-driven closure management, integration with the Incisive SimVision simulation debug environment, and support of SystemVerilog Assertions and SystemVerilog Direct Programming Interface.
"The proliferation of system-on-chips and the explosion of verification complexity have resulted in a thirst for more performance at the designer's desktop," said Steve Glaser, corporate vice president of marketing, Verification Division, Cadence. "The Xtreme III series was developed specifically to deliver acceleration to a broad set of design engineers by making it easy for them to use the advanced verification methodologies required to reach predictable verification closure."
Xtreme III systems are offered in two tiers: Xtreme III Desktop, an entry level product that supports simulation, acceleration and targetless emulation, and Xtreme III System that also offers in-circuit emulation capabilities. Both systems can accommodate up to 12 users simultaneously.
DNEPROPETROVSK, Ukraine – Novarm Ltd. has released the latest version of DipTrace 1.23, a PCB design software application package that is said to feature a PCB Layout module, powerful autorouter, schematic capture and component/pattern editors.
DipTrace's autorouter can route single-layer (bottom side) and multilayer circuit boards. There's also an option to autoroute a single-layer board with jumper wires.
The software has a shape-based copper pour system with different possible fill types and thermals to make plane layers or to reduce manufacturing costs by minimizing the amount of etching solution. Its design-rule checking checks the clearance between design objects, minimum size of tracks and through holes
DipTrace's autorouter can route single-layer (bottom side) and multilayer circuit boards. There's also an option to autoroute a single-layer board with jumper wires.
The software has a shape-based copper pour system with different possible fill types and thermals to make plane layers or to reduce manufacturing costs by minimizing the amount of etching solution. Its design-rule checking checks the clearance between design objects, minimum size of tracks and through holes
MUNICH, Germany and WESTFORD, MA – Zuken has announced the latest version of its desktop PCB design solution, CADSTAR 9.0. This release is said to feature usability and flexibility enhancements, along with functionality for adopting new technology. Simultaneously, Zuken has introduced the latest version of CADSTAR 3D, also with reported advancements in usability.
Improvements to the GUIs have resulted in graphical representations of every function assignment. ‘Trunk’ routing functionality within P.R.Editor XR has also been further enhanced to allow more flexibility. This includes providing designers with the ability to swap equivalent pins quickly and easily to improve routability. In addition, general usability developments have been made to the report generator, post drill files, DXF post processing, general menu and tool bars.
Improvements to the GUIs have resulted in graphical representations of every function assignment. ‘Trunk’ routing functionality within P.R.Editor XR has also been further enhanced to allow more flexibility. This includes providing designers with the ability to swap equivalent pins quickly and easily to improve routability. In addition, general usability developments have been made to the report generator, post drill files, DXF post processing, general menu and tool bars.
CADSTAR SI Verify includes upgrades to the via modelling function in order to provide more in-depth analysis details, and user defined n-port circuit models to take into account components such as filters and ferrite beads.
WILSONVILLE, OR – Mentor Graphics Corp. has released the latest version of its Board Station design flow for large, enterprise customers. The Board Station flow includes tools for design creation, layout and manufacture, and is designed to meet the requirements of enterprise design teams. This release is said to offer improved integration with the enterprise, as well as improved design productivity and 'what if' signal integrity analysis.
“Advances in PCB fabrication technologies, system performance and FPGA densities/pin counts, compounded by emerging government regulations such as RoHS, continue to challenge our most aggressive customers as they strive to meet competitive time-to-market goals,” said Dan Boncella, director of marketing, Systems Design Division at Mentor. “This new release of our Board Station flow addresses these challenges by continuing to tightly integrate our high speed pre- and post-layout analysis tools, library and data management, and adds PCB interactive routing productivity enhancements.”
This version of Board Station is said include the following enhancements:
- Library and data management - Tighter integration with DMS and added functionality to provide off-the-shelf RoHS design-for-compliance capabilities.
- Constraint editor system (CES) - Addition of electrical rules entry, layout and analysis functionality to complement the high-speed physical rules already provided.
- Signal integrity verification - Addition of the newly released ICX Pro Explorer functionality to the flow, our next generation high-speed constraint development tool.
- Design layout - Additional support for layout of flex boards, addition of trace glossing so designers can more closely control interactive routing on dense designs, hard and soft autorouting “fences” to help control routing around dense BGAs as opposed to through them, and additional gate and pin swapping capabilities to optimize layout.
- FPGA-on-Board - Improved integration of I/O Designer to accommodate high pin count and high performance FPGA implementation on the PCB.
“Advances in PCB fabrication technologies, system performance and FPGA densities/pin counts, compounded by emerging government regulations such as RoHS, continue to challenge our most aggressive customers as they strive to meet competitive time-to-market goals,” said Dan Boncella, director of marketing, Systems Design Division at Mentor. “This new release of our Board Station flow addresses these challenges by continuing to tightly integrate our high speed pre- and post-layout analysis tools, library and data management, and adds PCB interactive routing productivity enhancements.”
This version of Board Station is said include the following enhancements:
- Library and data management - Tighter integration with DMS and added functionality to provide off-the-shelf RoHS design-for-compliance capabilities.
- Constraint editor system (CES) - Addition of electrical rules entry, layout and analysis functionality to complement the high-speed physical rules already provided.
- Signal integrity verification - Addition of the newly released ICX Pro Explorer functionality to the flow, our next generation high-speed constraint development tool.
- Design layout - Additional support for layout of flex boards, addition of trace glossing so designers can more closely control interactive routing on dense designs, hard and soft autorouting “fences” to help control routing around dense BGAs as opposed to through them, and additional gate and pin swapping capabilities to optimize layout.
- FPGA-on-Board - Improved integration of I/O Designer to accommodate high pin count and high performance FPGA implementation on the PCB.
POPULAR
- Designing Printed Circuit Boards for the Internet of Things
- The Last Printed Circuit Plant in the US Closes Its Doors
- Are Transmission Line Signals in Printed Circuit Boards Different from Conductor Signals?
- Via-in-Pad Design Considerations for Bottom Terminated Components on PCB Assemblies
- Who Were Preece and Onderdonk?
Press Releases
- Atotech to Present New Products for Flex/Flex-Rigid PCB Production to Serve Current Market Demand at KPCA 2018
- Prototron Circuit Exhibits at SMTA Puget Sound Expo & Tech Forum
- Rogers Corporation to Offer Advanced Circuit Materials for Latest Amplifiers, Multilayer Designs & 5G Wireless at the Del Mar Electronic & Manufacturing Show
- Don Dupriest Elected to Chair Top IPC Standards Leadership Committee