“Process Development for Micro-Electronics Packaging with Direct Printed Additive Manufacturing”
Abstract: Using additive manufacturing as an alternative for packaging has not been taken seriously, but there is an opportunity to demonstrate the significant advantages of true 3D electronic packages by permitting the package to be the printed circuit board and by utilizing direct print and bare die approaches to print and structure diverse electronics. In order to build a device by implementing an additive, layering process, materials must be studied and characterized for repeatability and reliability of mechanical and electrical performance. This paper summarizes a study of some of the materials and the process used to build 3D structures using DPAM. Also described are variables that are adjusted to optimize a build with a DPAM process. A carbon nanotube – photopolymer composite, conductive ink, conductive adhesive and standalone photopolymer were tested for their individual electrical resistances, as well as the resistances when layered on each other. A single layer (~100µm thick) was dispensed then tested for its electrical resistance. The final build consists of three layers with a surface-mounted active component placed and electrically epoxied in place. (SMTA International, October 2012)
“3D Packaging for High Computing with Wide IO Processor-Memory Interface”
Abstract: Current interconnect technologies for package-on-package such as stacking with smaller sized solder balls, using solder-filled laser-drilled vias in the mold cap, or using organic interposers are not practically achieving high IO requirements, since the aspect ratios of these interconnects are limited. To address the gap in PoP interconnect density, a wirebond-based package stacking interconnect technology called Bond Via Array is presented that enables reduced pitch and a higher number of interconnects in the PoP perimeter stacking arrangement. The main technological challenges are identified and research results explained. The main challenges were forming freestanding wirebonds, molding the package while exposing the tips of the wirebonds, cleaning the wire tips and package stacking. Assembly results showed that the wire tips were within the desired positional accuracy and height, and the packages were stacked without any loss of yield. (SMTA International, October 2012)
“High-Density Integration of Carbon Nanotubes via Chemical Self-Assembly”
Abstract: Carbon nanotubes have potential in the development of high-speed and power-efficient logic applications. However, for such technologies to be viable, a high density of semiconducting nanotubes must be placed at precise locations on a substrate. Here, the authors show that ion-exchange chemistry can be used to fabricate arrays of individually positioned carbon nanotubes with a density as high as 1 × 109 cm−2 – two orders of magnitude higher than previous reports. With this approach, the authors assembled a high density of carbon-nanotube transistors in a conventional semiconductor fabrication line and then electrically tested more than 10,000 devices in a single chip. The ability to characterize such large distributions of nanotube devices is crucial for analyzing transistor performance, yield and semiconducting nanotube purity. (Nature Nanotechnology, Oct. 28, 2012)
Solder Joint Reliability
“Impact of Electrical Current on the Long-Term Reliability of Fine-Pitch Ball Grid Array Packages with Sn-Ag-Cu Solder Interconnects”
Author: Tae-Kyu Lee, Ph.D.
Abstract: The interaction between electrical current and long-term reliability of fine-pitch BGAs with Sn-3.0Ag-0.5Cu (wt.%) solder ball interconnects is investigated. In this study, 0.4mm fine-pitch packages with 300µm-diameter SnAgCu solder balls are used. Electrical current was applied under various conditions to two different package substrate surface finishes to compare the effects of chemically unmixed and mixed joint structures: a Cu/SAC305/Cu structure and a NiAu/SAC305/Cu structure, respectively. To study the thermal impact on thermal fatigue performance and long-term reliability, the samples were thermally cycled from 0° to 100°C with and without current stressing. Based on Weibull plots, characteristic lifetime was degraded for the mixed joint structure, but little degradation was observed for the unmixed joint structure. The microstructure evolution was observed during constant current stressing and current stressing during thermal cycling. Accelerated intermetallic precipitation depletion at the package-side interface was observed in NiAu/SAC305/Cu structures due to current stressing, which was identified as the potential reason for the degradation in the thermal cycling performance. (Journal of Electronic Materials, Oct. 28, 2012)
This column provides abstracts from recent industry conferences and company white papers. Our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.