For good or for bad, I am known as the creep corrosion expert. We have had this discussion before; it is not exactly the claim to fame I was expecting in life. I have other knowledge and talents but nothing deemed worthy of industry-wide recognition or my picture on the Wheaties box. I was a cog in the wheel during the microvoid fiasco. I know a heck of a lot about galvanic attack and nickel hyper-corrosion, and a thing or two about soldering. My chances of becoming a professional athlete are slim to none at this point in my life, though that was a childhood dream. My biking times are way too slow to get me noticed on the triathlon circuit, and I stay away from performance-enhancing drugs. I did just recently start incorporating chia seeds into my diet. (All the yogis are doing it, so I figured I would try.) I rode 7 minutes faster this weekend over last, but either way, I’m still slow on the bike. I am not ready for competitive yoga. Frankly, I feel competitive yoga defeats the purpose of quieting the mind and resisting the urge to judge, but I digress.
So that leaves me as a creep corrosion expert with quite a lot of knowledge on surface finishing in electronics. This has earned me a nice seat as a session chair at SMTA International. I enjoy this responsibility and am honored to be asked. I find this conference to be an inviting atmosphere. I am always learning and meeting new people. The discussions and sessions provoke participants from different market segments and with different responsibilities to review the latest issues with an effort to find answers to issues plaguing all of us. Now that IPC and SMTA have joined for this year’s conference, I think we can enhance these important discussions with a more formal outcome via IPC recognition and possibly new standards.
When I was tasked with resolving microvoids, it was a new defect that no one knew much about. There was no industry knowledge on what caused it and no standard for acceptance. Actually, there still isn’t. When I was tasked with resolving creep corrosion, it was a defect that no one had seen, and there was no standard for how to test for it. There was no documentation stating what level was acceptable. Actually, there still isn’t today. Lucky for me, microvoids are pretty well understood, and the means for how to control them are in place globally. Also, there is an organized group trying to replicate real-world corrosion defects in a controlled lab environment. It has not been easy, but I maintain hope. I know collaborative efforts will bring a quicker resolution.
With constant industry changes, including advanced designs and more mobility of electronics, there will always be a need for more standardization to guide the successful making of products. Recently, I have been thinking more about electronic packaging. Use of QFN components is exploding. Prismark stated that in 2013 the QFN has been the fastest-growing package outside of flip-chip scale. Many have turned to QFNs over BGAs due to higher cost, design and manufacturing difficulties associated with BGAs. They have found that they can avoid the difficulties associated with BGAs and still achieve the desired electrical performance with QFNs. Yet, there is a need for appropriate preconditioning and test methods to ensure the performance and reliability of this component style and to be sure we are all testing to the same criteria.
The process of singulating IC packages such as QFNs by either a sawing or punching operation results in exposed copper on the sidewalls. This exposed copper surface can oxidize and lead to poor or no solder wetting up the sidewall during the assembly operation (Figure 1). The consequence of this oxidized copper surface is either incomplete or no solder fillet formation during the PCB mounting operation, resulting in solder joint reliability concerns. Currently, Jedec and IPC assembly standards do not specify a toe fillet for assembly. However, several component manufacturers have requested a toe fillet solderability process, which would improve current QFN reliability by ensuring toe fillet solder coverage. Work has begun on this with input from all parties: chemical suppliers, merchant packagers, EMS and OEMs. Amkor has shown through simulations and actual test data generated by customers that fillets – if formed – can improve board level reliability as much as two times for a package with large die-to-package size ratio.2
This topic and many other interesting subjects will be reviewed at SMTA International this month in Fort Worth, TX. I’ll be there; it is my favorite conference of the year, with the most valuable technical discussions. Be forewarned: this is an environment of collaboration. Be prepared to make friends and get involved in some interesting discussions.
References
1. Vern Solberg, “PBD Design Principles for QFN and Other Bottom Termination Components,” IPC webinar, June 23, 2011.
2. A. Syed and W. Kang, “Board Level Assembly and Reliability Considerations for QFN Type Packages,” Amkor white paper.
Lenora Toscano is final finish product manager at MacDermid (macdermid.com); This email address is being protected from spambots. You need JavaScript enabled to view it..