The demand for signal integrity engineers is on the rise, but universities have made slow progress in training for today’s power and signal integrity challenges.
As part of the strategy to reduce costs at all levels of product development, engineering managers have started to re-organize their teams, looking for breakthroughs in design and technology methodologies. A good understanding of the new engineering environment is essential in getting the right teams in the right places to face the challenges in product development cost, schedules and technology innovations. Signal integrity (SI) is one of the specialty fields that is often overlooked and misplaced in the organizations. While SI activities have been related to system design for many years, the current technology advancements connect SI engineers to multiple areas in the system design.
The push for speed, reduction of power usage and easy-design interface have undergone some industry standardization over the past few years. Differential signaling is getting more traction due to higher speed requirements; serial communication ports (SERDES interfaces) are getting broader use. Platform design teams have grown in size. The design managers now need SI engineers on their teams, closely working with logic design and manufacturing engineers. SI consideration inside the integrated circuits is a very significant job, but it is the same on system boards for the same reasons.The PCI Express’ popularity, due to the performance that can be achieved on an interconnect and the benefits on cost and power requirements, has easily replaced the conventional (parallel) PCI interface from the computer systems. However, serial memory interface, supporting fully buffered dual in-line memory modules (DIMMs) (FBDIMMs), has not been able to replace the conventional parallel memory interfaces. The parallel memory interface has been in the systems for many years, requiring higher speeds in every new system. In FIGURE 1, the evolution of memory architectures is shown, with DDR4 on estimated market dates.
The memory subsystems require different sizes and configurations depending on the market and application. Server systems require high-speed memory that is scalable in size, and mobile platforms, in return, require higher speeds to the degree that the system permits. Memory modules come in different form-factors: DIMMS for high-performance systems and SODIMMs for mobile and embedded systems. Additionally, there are multiple types (raw cards) of DIMMs and SODIMMs, depending on the speed and/or amount of memory desired, connecting memory devices in 1-rank, 2-rank and recently 4-rank architectures. Each is laid out based on extensive signal quality and timing analysis, and some systems (for example, embedded systems) may require memory implementation down on the system board.
For memory interface signals, the memory devices and memory modules are all standard, and standardization is driven by JEDEC. However, every new system design is likely to require a different memory configuration. Regardless of the standardization activity on signaling and interconnect types, due to demand in higher performance technology and variations in applications, power integrity and signal integrity have been growing into a complex engineering expertise field.
Once it is designed, the silicon IO has to work on a board. That brings up the methodology of how a new IO design can fit into other parts of the system. The silicon would not work by itself because the packaging is an integral part of the silicon product. FIGURE 2 depicts the way the components of a mainstream system were designed, composed of three rather disjointed design activities.
Cost and available technology were also what drove a package design. Packages were standard products, available for silicon designs that were productized probably with no specific silicon requirements – except possibly the number of pins. Once the silicon design was completed, one of the standard packages that would best fit the silicon requirements would be picked and silicon would be packaged. Then, the system designers would take over and develop the system requirements with decisions as to which packaged silicon products to use in the system.
The technical challenges, along with cost and schedule (time-to-market) pressures from the market, triggered a transition in the engineering organizations. The transition to a new system design strategy has been evolving (and is still in progress) since the beginning of 2000, by merging three major design areas: IO buffer design, package design and board interconnect design.
FIGURE 3 describes the new high-level design concept in regards to power integrity and signal integrity in systems. The power delivery analysis is performed while the package is being designed, in conjunction with the development of the IO buffer power requirements and board power delivery. The SI analysis starts at the IO buffer pad on the silicon and is completed through the package components and board interconnects at the destination silicon IO buffer pad. While analyzing one section of the signal path, any corrections/changes made in the design of that section will probably affect other sections of the signal path. Therefore, it is an essential design practice that the entire path be analyzed iteratively.
Why? Here is the short technical answer: v(t) = L(di/dt) in time-domain or v(w) = jwLI(w) in frequency-domain, describing the behavior of high-speed signals on interconnects. The high-density interconnects of today’s packages and boards are all predominantly inductive. An interconnect of almost any length is to cause, in terms of power integrity and signal integrity, changes in the signals’ quality and timing at speeds of signals we are dealing with today. The electrical lengths of rise and fall times of today’s signals are around 50 pS to 100 pS. For interconnects, the length that would “see” the “transmission line effects” is about 1 inch, with such speeds of the signals. Today’s packages are densely routed, and all interconnects, on such package substrates and system boards, are to be entirely considered transmission lines. Therefore, signals traveling down such interconnects need to be analyzed for signal integrity and timing.
For an acceptable level of signal integrity, signal return path has to be contiguous. However, more often than not, return paths on the packages and boards of the signals are split due to multiple interfaces being routed in a small area. This changes signal layers with or without a return path or possibly in different power domains. Issues with such return paths are well documented.1
The challenges revolve around technical, cost and schedule issues. The first step the industry needs to take concerns scheduling. Engineering groups within companies need to get organized to take the new challenges. The design organizations that may have been previously disjoint, must now be reorganized as a single entity, as suggested in FIGURE 4, in order to increase/enhance coordination among the activities. One focus point for all groups is engineering.
The advantage of a purpose-driven organization of the type shown in Figure 4, is that the design groups are closely coupled under the same management, enabling efficient coordination and synchronization of the engineering activities to ensure a high-quality product, preventing cross-organizational hindrances that may eventually delay the progress (and schedule) of the engineering activities and risk the quality of the product due to different priorities among groups. The technical groups would still be required to interface with the larger product group(s) to make sure what they are designing is feasible in terms of overall system cost, performance, manufacturability and other technical requirements.
Technical knowledge and expertise is the key ingredient in such an organization. So, the engineers need to be trained to do the job correctly, which brings us to the second step we need to take – education. Given today’s engineering curriculums in the universities, there aren’t enough SI engineers to meet the industry’s demand. Over the years, the need for more experienced engineers who have experience in the PI/SI challenges related to package and board design has grown exponentially. The companies have been training their own engineers, frequently taking advantage of classes offered by SI experts who are well-known in the global industry. Companies that can afford hiring new graduates have been training and internally growing SI engineers. These companies also provide complete system design guidelines to the system houses that have no, or very little, SI resources. This model helps companies in two ways: the company’s design-related IPs are not revealed and system houses (specifically, small system manufacturers) save funding that they would otherwise have to allocate for signal integrity, and this shortens time-to-market.
Nevertheless, the demand for SI engineers is on the rise, and universities will finally realize they need to get in on SI training. The University of South Carolina is one of the educational organizations2 that has taken the lead by co-operating with Intel Corporation to develop an SI curriculum and to offer graduate degrees. There are several other universities worldwide that offer courses on signal integrity at different levels. Although there is progress, it is still not enough. It takes an engineer at least two year of on-the-job training.
Power integrity and signal integrity engineering adds to the system development cost which is on the rise as the performance requirements on the interfaces keep going up. The standardization on the interface signaling has, to some degree, reduced and simplified the SI process during the design of the system components as explained above. However, an ever-increasing speed requirement is opening the door to new and previously unexplored technological challenges. For example, the new IO buffer has to be modeled and analyzed with the new package and board design environment. And this brings us to the third step we need to take to enable a power-integrity and signal-integrity organization.
Power integrity and signal integrity tool development is trying to catch up with the need for more performance and accuracy. Modeling requirements for the components has become a challenge. The higher the speed on the interface, the higher accuracy in modeling is required in the analysis of the signaling. Therefore, the more complex the modeling effort becomes. For example, a PCIe Gen2 interface (and definitely Gen3) requires analysis including modeling of variations in dielectric glass fiber weave3 because at high speeds, the weave effect results in a significant difference in common mode noise in the interface that would not be so important at lower speeds.
Modeling has gone through several stages of life, with the current status as follows.
For IO buffer circuits:
Spice modeling at the transistor circuit level is to remain the golden standard, as advanced circuit parameters can be included that other modeling standards cannot model; however, IP protection is a serious drawback.
IBIS modeling has been an industry standard, especially because it allows fast simulations (compared to spice tools).
However, as a standard, it falls short of meeting the technology requirements. It can’t currently model complex parameters of IO buffer circuits, though there are studies in the works to create extensions of IBIS for use in complex circuit modeling.
Other types of behavioral modeling are a good alternative if simulation tools are ready to accept it.
For interconnects of packages and boards:
Lumped or distributed transmission line models at lower frequencies (up to 1 GHz) worked fine.
S-parameter models produce higher accuracy results, especially at higher frequencies (higher than 1 GHz).
Coupled line models definitely results in higher accuracy for a densely routed interconnect environment
The modeling software tools using 3D algorithms are more commonly used today for accuracy in models, compared to previously available tools. The simulation software tool is one of the most important factors in the efficiency of an SI organization. Simulation methodologies are developed by experienced engineers, and those methodologies are accepted as the process for the designs that the group may be assigned to analyze. There are many simulation software tools available in the industry, and engineers, in general, use different tools for different simulation jobs – there isn’t one tool that does it all. There are a few good simulation tools on the market, but their accuracy is often questioned.4
The software tool chosen must include many features that would augment the engineer’s analysis capability. As design complexity increases, the amount of analyses and the number of simulations required go up exponentially. One of the solutions is to understand the capabilities of the tools being used and to provide as much automation as possible for the processing of the data generated. This is possible with consistent design/analysis methodologies and tool capabilities, enabling the reuse of setups for interface types.
Under such demanding conditions, the software tool of choice would be one that is most suitable to the design and simulation methodologies being followed. The list of desirable features for a tool includes:
- accuracy and speed (simulation execution performance of the tool)
- simulation environment setup (configuring the tool for use in specific interface simulation)
- model availability and usability by the tool (handling of different types of models in the tool)
- types of simulations (frequency-domain and time-domain)
- advanced analysis methodologies (for example, prediction of a worst-case pattern for crosstalk and ISI, prediction of parameters causing worst-case operating conditions)
- measurements (calculations)
- results processing (developing the final design guide for the product)
Such stringent requirements on tools have created a highly competitive market in which many EDA companies have a stake. Furthermore, depending on the technologies being developed, some large companies develop their own internal tools, mostly to process simulation results in different ways to complete their analyses.
The new designs at silicon level and system level are “validated” in the labs, which add to product development cost; high-performance measuring equipment is costly. However, by characterizing the new IO buffer behavior in the lab, the effect of packaging on signals and signal quality on the system board interconnects provides the engineer with a means to ensure the new models. The new methodologies and the new tools used to analyze and to design the interface were correct.
The goal is to make sure the product is designed right the first time (at least in terms of power integrity and signal integrity). Organizations working, as described above, have been successful in designing “right the first time” products faster and for less cost. Yes, this is still a high-cost engineering organization, but without it, post-production problems can be even more costly.
Power and signal integrity analysis is required on any design with today’s technologies. As a growing engineering field, challenges must be addressed. High-tech companies that design systems and system components need power and signal integrity engineering organizations that enhance communication among the groups designing IO buffer circuits and interconnects (packaging and system boards).
As the demand for SI engineers rises, universities must keep up with demand for power and signal integrity. EDA companies can enable technology development by offering high accuracy simulation tools, possibly partnering with design houses that are heavily investing in future technologies. All this enforces innovations in the work of the engineers, further resulting in reduction in cost and enhancement of productivity of the organization. PCD&F
REFERENCES
1. “Analysis of Crosstalk between Signals Routed over Discontinuous Reference Plane,” Mustafa Yousuf, Brahim Bensalem, Naveid Rahmatullah, DesignCon 2009, Santa Clara, CA, USA, 2009.
2. www.ee.sc.edu/research/SignalIntegrity
3. “Simulation Fiber Weave Effect,” Chris Herrick, Thomas Buck and Ruihua Ding, Printed Circuit Design & Fab, May 2009.
4. “Accuracy of Transmission Line Simulators,” Eric Bogatin, Printed Circuit Design & Fab, May 2009.
Hal Katircioglu is manager,
Platform Engineering Signal Integrity Group, ECG, Intel Corporation;
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