Microvias are more reliable than through holes, so adding HDI to the design can improve reliability and reduce cost.

Meeting the predictable but challenging market-defined needs of high-density (HD) PCBs requires new flexible design approaches that provide higher I/O densities, higher performance and lower costs than previously available solutions. In this paper, the four common high-density interconnect (HDI) via architectures are compared to determine how well each meets these diametrically opposed requirements. The four via architectures to be examined are:

• Drilled sequential lamination
• Staggered sequential microvia build-up
• Stacked sequential microvia build-up
• Co-laminated any layer microvia build-up.
  

The basis for comparison is looking at the complexity of the fabrication process and expected yields. Design for manufacturing (DfM) now focuses on yield management (YM), and via structure is a major contributor to yield loss. This is contrasted to the resulting density, design constrains and I/Os per square inch achieved.

Yield issues are more difficult to pin down because they are dependent on a number of variables and are largely statistically driven (i.e., the greater the occurrence of a certain configuration, the greater the likelihood of a board failure). This paper will propose a simplification of the Wiebull Defect Density model as the basis for predicting the first-pass yield (FPY) of new HDI boards in manufacturing.

Introduction

An excellent way to describe interconnect complexity and density changes is with the Interconnect Technology Map, Figure 1. To describe the component complexity of an assembly, the total component connections (I/Os), including both sides of an assembly as well as edge fingers or contacts, are divided by the total number of components of the assembly. The resulting average leads (I/Os) per part provide the X-axis of the chart. As ICs become more complex and their I/Os increase, this number naturally goes up.

When the chart is used to describe surface-mount assemblies, the Y-axis describes how complex it is to assemble the board by the number of components per square inch or per square centimeter. This is component density. As the parts become smaller and closer together, or the substrates get smaller, this number naturally goes up. A second assembly measure is average leads (I/Os) per square inch or per square centimeter. This is the X-axis multiplied times the Y-axis.

By charting products of a particular type over time, an analysis will show how the interconnect technology is changing, its rate of change and the direction of those changes. An example is given in Figure 1. The evolution of this board as a 16-layer multilayer PCB (a. & b.) to a 12-layer sequentially laminated MCM-L with blind and buried drilled vias (b.+) to its final form as an 8-layer HDI with sequential build-up microvias (c.) is seen in Figure 1.

The area called the Region of Advanced Technologies is where calculations and data have shown that it is necessary to have a blind and buried via structure. Therefore, this is the through-hole barrier or wall of HDI! Cross this, and it now becomes cost effective to use HDI. Move too far, and it becomes a necessity.

The HDI Vintage Chart

HDI technologies in use today are comprised of three factors: the dielectric materials, the methods of interstitial via hole (IVH) formation and the method of metallization of the Z-axis via connections. Twenty-one different HDI processes are either currently in use or have been used recently, as seen in Figure 2.

There are eight different general dielectric materials currently being used or used in recent HDI processes. IPC slash sheets such as IPC-4101B and IPC-4104A cover many of these, but many are not yet specified by IPC standards. These are:

• Photosensitive liquid dielectrics
• Photosensitive dry-film dielectrics
• Polyimide flexible film
• Thermally cured dry films
• Thermally cured liquid dielectrics
• Resin coated copper foil (RCC)
• Conventional FR-4 cores and prepregs
• Thermoplastics.
  

There are seven different methods of forming the IVHs used in either current or past HDI processes. Laser drilling is the most prominent, but the other six come into use also:

1. Photo process to define vias in photo-dielectrics
2. Various laser drilling methods, including UV-Yag, UV-excimer and CO2
3. Mechanical drilling
4. Plasma drilling
5. Screen printing of via pastes
6. Photoimaging and etch of solid vias
7. Tool foil.

There are four different methods of metallizing the IVHs used in current or past HDI processes:

1. Fully additive electroless copper
2. Conventional electroless and electroplating copper
3. Conductive pastes
4. Fabricating solid metal vias.

This paper will examine four of these blind and buried stackups:

1. TV1: drilled sequential lamination
2. TV2: staggered sequential microvia build-up
3. TV3: stacked sequential microvia build-up
4. TV4: co-laminated any-layer microvia build-up.

Alternative Stackups Using Blind and Buried Vias

Four common approaches for the blind and buried via stackups were selected. Each structure used the same traces and spaces, as well as material type and thicknesses to keep the impedances within specification. The boards’ sizes and layers were reduced to the smallest that could be autorouted to 100% completion and that the via structure would permit. These are shown in Figure 3 and described here.

TV1: Drilled Sequential Lamination

The only practical way to wire up a higher density board (average pins/square inch > 120) and not use microvias is with drilled sequential lamination. Figure 3a shows the 12-layer multilayer stackup composed of two 4-layer multilayers, drilled and plated and then laminated to two rigid cores with three pieces of prepreg. Board size has been reduced 23% to 50 sq. in. and drill sized reduced to a 0.008˝ finished hole size (FHS) for the four-layer composite multilayers but remains at 0.010˝ FHS for the through-holes.

TV2: Staggered Sequential Microvia Build-up

The staggered via IPC Type III stackup is the most popular and versatile. Figure 3b shows the 10-layer multilayer stackup comprised of one-buildup layer on each side of an eight-layer multilayer board, mechanical/laser drilled and plated and then laminated to a piece of prepreg and foil. Board size has been reduced 30.8% to 45 sq. in. and microvia drill size to a 0.006˝ FHS for the two buildup layers. The composite multilayer hole size remains at a 0.010˝ FHS for the through holes and buried vias.

TV3: Stacked Sequential Microvia Build-up

The stacked via IPC Type III stackup is now becoming popular in North America. Figure 3c shows the eight-layer multilayer stackup composed of two-buildup layers on each side of a four-layer multilayer, mechanical/laser drilled and plated and then laminated twice to pieces of prepreg and foil. Board size has been reduced 43.1% to 37 sq. in. and the microvia drill size to 0.006˝ FHS for the two buildup layers. The composite multilayer remains at 0.010˝ FHS for the through holes and buried vias.

TV4: Co-Laminated Any Layer Microvia Build-up

The any-layer via is an IPC Type VI stackup. This type is popular in Japan and Asia for its high density. Nearly nine of the HDI Vintages in Figure 2 are this type. Figure 3d shows the eight-layer multilayer stackup composed of four double-sided layer pair cores. Each is mechanically or laser drilled and plated, etched, and then tested. These are then laminated with prepreg that also has vias. This unique scheme allows any layer to connect to any other layer. Board size has been reduced 50.8% to 32 sq. in. and the microvia drill size to a 0.006˝ FHS. This stackup does not have any through holes!

PCB Basis

A 16-layer through-hole board was selected as the printed circuit basis for the different design strategies. The 1517 pin FPBGA with 50 Ω single-ended drivers and 100 Ω differential data pairs dominates the board. Two other BGAs of 940 pins and 498 pins also complicate the design. These are connected to 16 flash memories with 144 pins at 0.8 mm. The multilayer board is 10.0˝ x 7.8˝ with a full 1.5V power plane and a 2.5V, 1.25V, 5V split power plane. A top view can be seen in Figure 4.

Setting Up HDI Routing

Using an EDA tool with HDI design capability, setting up any of the various 21 different HDI architectures was very simple. The Constraint Editor System (CES) allowed impedance, crosstalk, wiring, spacing and timing to be easily specified for all the high-speed single-end and differential nets, as well as by “Net Class” and “I/O” constraints.

Figure 5 shows three of the “configuration” menus that set up the different blind and buried via structures. Menu a is the blind/buried/through-hole via span as well as via diameter and electrical characteristics. Menu b holds the via-to-via clearances for stacked, inset or staggered vias. Menu c is the dynamic planes generator for controlling planes spacing, copper pouring and electrical characteristics.

The three complex BGAs were all fanned-out semi-automatically using the unique blind/buried via available for that structure. The combination of layer-stackup and microvia placement eliminated many of the larger drilled through-holes and drilled buried vias. A circuit copy & place command was used to replicate the breakout pattern keeping in mind the layer bias so that the autorouter would pick up the trace hangars.

The autorouter was optimized for each type of blind/buried via structure and layer-pairing. Autorouting was performed first by critical nets and build-up layers, then tuned and smoothed. After the maximum utilization of the blind vias, the larger through-hole and buried vias were allowed. The fact that the autorouter could push and shove traces and microvias made for the most flexibility in their being placed but in not disturbing the critical nets.

Performance of Microvias

The results of the four sets of design runs were quite remarkable. Via geometry, clearances and stackup have a profound affect on breakout and routing. This was the overriding variable that permitted a smaller board with fewer layers. With fewer through-holes, innerlayer routing density was two to three times greater because of the additional space freed up with the removal of the large drilled holes. The alternative stackups of the HDI boards also allowed microvias to replace as many as 45% of the through holes. The routing layer-pairs of X-Y using microvias as layer-transition greatly reduced the need for buried vias and through holes. The results can be seen in Table 1.

Summary of Through-Hole versus HDI Structures

To summarize the positive effect blind and buried microvias have on board size, layers and density, the chart in FIGURE 6 has been prepared. This is a summary of 10 years of through hole to HDI design and fabrication benchmarking. Each main Structure Column represents a Via Architecture, from through holes to Type I, Type II and Type II HDI stackups. These columns have been further separated into two metrics: Relative Cost Index (RCI) and Density (DEN). Total layers separate the rows.

The RCI metric contains real production quotations and prices from around the world for high-volume production. The prices are all normalized to the price of the eight-layer through-hole boards from China. Hence, the relative cost as an index. The DEN metric is the average number of component, connector and test pins (leads) on both sides of the board divided by the board’s length and width. This is the typical number of component pins that that size of board with that number of layers can support. Boards with more power planes or extremely complex BGAs (> 700 pins) may require more layers than represented here.

The typical HDI board, when benchmarked, shows a design approach of adding layers for conventional through-hole routing, then moving to the right of the chart in Figure 6 [PDF format] (density and relative cost index for through hole to various HDI structures) to avoid via starvation. This results in an instant RCI increase of 30% to 40%. The alternative, as described in this paper, can be found along the diagonal dashed line in Figure 6, using HDI to reduce the size of the board and the total layers. This has the effect of reducing the RCI by 30% to 50%. The results of the routing test on the Test Vehicles 2 through 4 verify this observation.

First-Pass Yield

The fabrication capability coefficient (FCC) is computed from a fabricator’s electrical test data, the first-pass yield (FPY). This is the yield of production before any repair or rework. PCB yield data is not “normally distributed;” it is a “gamma distribution.” This is only common-sense, as you can have a typically high-yielding board with some bad production runs; the resulting mean and standard deviation would reflect the lower yield data but on the “plus” side, you cannot have greater than 100% yield. Thus, the normal mean and standard deviation does introduce some errors that we will ignore for the calculation of the FCC. If you have the ability to calculate and insert a gamma-distribution average, by all means do it.

Fabrication Capability

The basic truth about PCBs, substrates and hybrid circuits is that design factors have a cumulative effect on manufacturing yield. These factors all affect the ability to produce the product. Specifications may be selected that individually do not adversely affect yields, but cumulatively can dramatically reduce yield and profitability. A simple algorithm is available3 that collects these factors into a single metric called the Complexity Index (CI). It is given in Equation 1 below:

Where:
Area = top area of the substrate to be designed
Holes = total number of drilled holes – blind, buried and through
Holes/unit area = holes divided by board area
Trace width = the minimum trace width
Layers = the total number of layers in the substrate
Annular ring = ½ the difference between the via land and the hole diameter
Hole diameter = finished hole size.

There is no standard for the Complexity Index. It is whatever fits your data the best. You need to experiment to find what definition of the CI equation gives the highest r2 value (goodness of fit).

FPY is affected primarily by the physical attributes of the board; parametric panels (PCQR2) can quantify these. But random effects also affect FPY-like handling, operator training, equipment maintenance, production shifts and unexpected events. These show up in the high variability of the yield predictions.

First-Pass Yield Calculations

The FPY equation is derived from the Wiebull probability failure equations4. This equation is of a more general form of the equation typically used to predict ASIC yields by defect density (typically, A=1 for ASICs) and provided in Equation 2 as:

Where:
FPY = first-pass yield
CI = complexity index
A, B = Fabrication Capability Coefficients

To determine the constants A and B in Equation 2, a fabricator must characterize his manufacturing process by selecting a number of printed circuits currently being produced (Table 2a) and having various complexity indexes, hopefully some low, medium and high. The first-pass yield (at electrical test without repair) of these printed circuits for several production runs is recorded (Table 2b). A statistical software program, such as Microsoft Excel, that has a model-based regression analysis is then employed to determine the FCC constants A and B, from this model, for the particular fabricator (Table 2c).

Constant A determines the slope at the inflection of the yield curve, and constant B determines the X-axis location of the inflection (Table 2d). The confidence level in yield predictability is determined by the statistical margin of error in the calculation of A and B.

Conclusion

The results in Table 1 show the improvements that blind and buried vias provide in layer and size reduction. The relative costs are taken from Table 1 by multiplying the RCI by the board size. Also important is the reduction in drilled holes since this is a major influence on the complexity index and FPY. When the relative costs are divided by FPY, the results are seen in Table 3. The more complex HDI via structures enable smaller boards with fewer layers and fewer drilled holes. TV1 has a 29.3% savings over the through-hole version, but TV2 is a 49.1% reduction; TV3 is a 58.0% reduction; and TV4 is the largest with a 62.9% reduction in cost. What isn’t taken into account here is the improvement in reliability that fewer through holes with a lower aspect ratio (due to thinner boards) provide. Microvias with their extremely low aspect ratio (AR < 1.0) are shown to be many times more reliable than through holes. PCD&F

References

1. Printed Circuit Handbook 5th Edition, Coombs, McGraw-Hill, 2001, pp. 1.5
2. Printed Circuit Handbook 6th Edition, Coombs, McGraw-Hill, 2007, pp. 23.2
3. “Calculate Your Fabrication Capability Coefficient,” Happy Thoughts, CircuiTree, Feb 15, 2006, BNP, pp. 23.5
4. “The Need For Statistical Tools,” Happy Thoughts, CircuiTree, Oct. 15, 2002, BNP, pp. 23.5