Designing a PCB Stackup Print E-mail
Written by Patrick Carrier   
Monday, 09 May 2011 21:44

Five steps to manufacturable, reliable boards.

Designing a stackup for a printed circuit board is all about tradeoffs. In many cases the primary design consideration is cost, resulting in designing the board using as few layers as possible. But the board also has to work, so signal integrity, power integrity, electromagnetic compatibility (EMC), thermal concerns, and manufacturability must be taken into account. Let’s step through the process.

1. Determine the number of layers and thicknesses. Often this is an iterative process between the electrical engineer, mechanical engineer and board designer. It usually begins with a mechanical constraint for the board thickness. Then the board designer determines the minimum number of routing layers needed, and the EE tries to fit all those routing layers into the total board thickness to maintain the right impedance. Impedance is what drives all the dielectric thicknesses in the board, and in order to understand how, some basics of trace impedance must be understood. Figure 1 shows the three main factors in determining trace impedance: trace width (W), height above the reference plane (H), and dielectric constant (∑r). Trace impedance goes up as H goes up, and impedance goes down as W and ∑r go up.



The minimum manufacturable trace width, without incurring extra cost, is usually 0.004" on 0.5 oz. copper. This is usually the starting point for determining layer height. Since the highest impedance is obtained by using the minimum trace width and maximum dielectric height, the dielectric height is set by the highest impedance needed for the layer using a 0.004" trace width. For instance, if the maximum impedance needed on a given layer is 60Ω, the dielectric height for that layer would be set to about 0.005", since a 0.004" trace with a 0.005" dielectric height would be 60Ω (given an ∑r of about 3.6). These numbers can be determined using a field solver (Figure 2). In addition to dielectric height and trace width, dielectric constant (∑r) is the other determinant of impedance, and is usually set by the PCB substrate material. However, ∑r can vary with different dielectric thicknesses, due to variations in glass and resin content. Typical values for an FR-4 substrate range between 3.5 and 4.5, so it is important to talk to the board manufacturer to get the right values. Also, if determining impedance for differential traces, the spacing between the traces must also be taken into account.



Other electrical constraints that drive the number of layers and thicknesses, particularly for planes, are power integrity and EMC. To meet EMC requirements, signals must have a solid reference plane, preferably ground. This means that in the layer stack, each signal layer must have a corresponding plane layer, and these can be shared. For power integrity, it is also preferred to have planes in pairs in the stackup, with power planes adjacent to ground planes, and as close as possible. Further, having those planes as close to the surface as possible, where the decoupling capacitors are mounted, is ideal. The typical copper weight used for plane layers is 1 oz. or more to handle the current carrying requirements for power and return, as opposed to 0.5 oz. for signal layers.

2. Determine trace widths and spacing. Once the number of layers and thicknesses is determined, the appropriate trace width for each impedance on each layer must be determined. This is usually just a matter of putting the desired impedance into the field solver and solving for width. It becomes a little more complicated when you have differential pairs, since a fourth variable – spacing between traces – is the other main determinant of impedance. You can solve for trace spacing or trace width. A Stackup Editor (Figure 2) can solve for both using the generated curve.

In most cases, use whatever trace width gives the highest impedance on a given layer, and determine the spacing. This gives the most differential coupling. However, most differential trace pairs are for multi-Gigabit SerDes busses, where one of the main concerns is loss. So, wider traces can be used, but to maintain the right impedance, larger dielectric heights would be needed (or greater spacing between traces). So, there are often tradeoffs to be made insofar as loss. Larger dielectric heights can be used to meet target impedances, but at the cost of routing density.

Another design concern affected by spacing is crosstalk. Crosstalk is the coupling of energy between traces. The greater the spacing, the less energy is coupled. A good typical value to use for spacing is about three times the dielectric height. Often, this number needs to be lower, and can be, but knowledge of total design margin through simulation is needed to make that assessment. In some cases, a spacing of greater than three times the dielectric height is needed, such as spacing between high-voltage aggressors and lower-voltage high-speed signals.

3. Specify tolerances. Once the layers, traces, and spacings are set, specify some tolerances to the design. Typical values used are 10%. It is good to actually simulate the effects of variations in trace width and dielectric height, as they will change the impedance, losses and crosstalk, and ultimately determine worst-case design margins.

4. Submit the stackup to your manufacturer and 5. Adjust target numbers as needed. It is very important to design a stackup that is manufacturable and aligns with the manufacturer’s process. Having a good idea of the material properties to be used in the stackup is essential to making sure the final design performs as expected.

Patrick Carrier is a technical marketing engineer for high-speed PCB analysis tools at Mentor Graphics (mentor.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Last Updated on Monday, 09 May 2011 22:30
 

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