Dual Row QFNs: Friend or Foe? Print E-mail
Written by W. Scott Fillebrown   
Tuesday, 01 October 2013 05:01

How to prevent the space-saving parts from causing headaches at assembly.

From time to time comes a new twist on an old technology. That is the case for our friend, the QFN. The new twist is a second row, thus the name dual-row QFN. Loved by space-conscious electrical engineers, it many times is a thorn in the assembler’s side.

The assembly issues are related to both the design and the actual fabrication of the board. A few examples of some of the issues that an assembler may face follow:

  • Traces between adjacent pads: tight spacing.
  • Solder mask registration: Ensure solder mask does not encroach the top of the pad (screen printing issue) and ensure all traces running between adjacent pads are covered, including the edges (prevents bridging). There should be a minimum of 1 mil of solder mask on the FR-4 surface from the edge of the trace. This may lead to the use of laser direct imaging (LDI) as opposed to a liquid photoimageable (LPI) solder mask.
  • Unequal PCB solder pad sizes between the inner and outer rows of pads can cause the part to solder to one row but not to the other row. During reflow, solder will coalesce, and unequal solder paste volume can cause one of the rows not to solder, resulting in component lift.
  • Inconsistent stencil apertures can cause skewing.
  • Care should be taken when determining the amount of solder for thermal attachment of dual-row QFNs with thermal pads. Improper solder volume can cause the component to lift and not make connection to the I/O pads.

Most of these issues can be significantly reduced or even eliminated through proper design.

Many packages permit room for vias between the thermal pad and the inside row. Issues arise when there is not enough room to escape the inner row through vias. The spacing of the pins can cause a neck down or thin traces throughout the design. The simplest method is to divide the edge-to-edge spacing of the pins by three; e.g., edge to edge of 9 would allow a 3 mil trace with 3 mil spacing to pin. If the trace is smaller than the common denominator, simply subtract the trace width and divide by two.

The spacing and trace widths should be verified with the fabricator to prevent delays during PCB fabrication. (LDI solder mask is preferred to maintain the webbing and permit a tighter tolerance of solder mask registration.) Typical solder mask oversize is 2 mils per side. This permits just 1 mil of solder mask to extend over the trace; therefore, the tighter tolerance of LDI is needed to prevent the registration tolerance from exposing a trace.

[Ed.: To enlarge the figure, right-click on it, then click View Image, then left-click on the figure.]

W. Scott Fillebrown is president and CEO of ACD (acdusa.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it . His column runs bimonthly.

Last Updated on Wednesday, 02 October 2013 00:54
 

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