Reliability Testing for Stacked Microvias in PWBs Print E-mail
Written by W. Scott Fillebrown   
Thursday, 01 August 2013 06:14

Design considerations for multi-level HDI.

Traditional single-level microvia structures generally are considered the most robust type of interconnection within a printed circuit board substrate. However, rapid implementation of high-density interconnect technology now commonly requires two, three or even four levels of microvias sequentially processed into the product.
Stacked microvias require duplicating and/or additional process steps in fabrication, including filling of the microvia, which establishes an ability to sequentially ablate additional vias into a structure containing microvias stacked on both sides of the substrate (Figure 1).

Recent OEM-funded reliability testing has confirmed that by increasing the levels (stack height), these structures are proving less reliable when compared to their single- or double-level counterparts. False positive results have been recorded on products tested with traditional thermal shock testing methodology (cycling between -40° and 125° or 145°C).1 Consequently, many companies are incurring product failures, resulting in increased costs associated with replacing the boards, components and added labor. Ranking the inherent reliability of three- and four-stack structures to other interconnects like plated through-holes or blind or buried vias may need to be reconsidered in future reliability test programs.

The introduction of multi-level microvia structures has taken place in parallel with increases in assembly temperatures, and the combined influence has resulted in greater strain applied to the interconnect structures and surrounding materials. Elevated assembly (and rework) temperatures reduce the reliability of interconnect structures and increase the risk of microvia and material failures, causing microvias to fail in response to the thermal excursion associated with assembly and end-use environment. Pb-free assembly and rework temperatures increase the stress experienced by the board substrate. These higher thermal excursions degrade the reliability of all interconnections and materials. The reliability of microvia structures used to meet the challenges of HDI applications must be assessed following exposure to Pb-free soldering.

As vias are added to the structure, the stress levels are increased relative to the increased dielectric distance between the upper capture pad and lower target pad. The focus of the stress concentrations are distributed over a wider range of interconnections, primarily any interface between each two levels of microvias (Figure 2).



There are new developments for establishing microvia interconnect reliability using elevated thermal cycle testing of representative coupons. Improvements in testing accuracy are achieved by means of increased sensitivity in the test vehicle (coupon) designs, improved test methods and more accurate failure analysis. Thermal cycle testing of microvias is effective at 190°C for FR-4-based dielectric materials, and these increased temperatures effectively demonstrate that robust structures can survive beyond 3,000 thermal cycles.

As you know, I believe the design process is a team effort. When approaching any leading-edge technology, include your board manufacturer in your design team. That is exactly what was done in this column, and I would like to thank Streamline Circuits for their input.

References

1. Bill Birch, “Reliability Testing for Microvias in Printed Wire Boards,” Circuit World, vol. 35 no. 4, 1999.

W. Scott Fillebrown is president and CEO of ACD ( This e-mail address is being protected from spambots. You need JavaScript enabled to view it ). His column runs bimonthly.

Last Updated on Thursday, 01 August 2013 17:50
 

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