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Written by Mike Buetow and Chelsey Drysdale   
Thursday, 01 March 2012 23:36


“Package Substrate Advancements through Improved Adhesion of Electroless Copper to Dielectrics”

Authors: Robin Taylor, Dr. Lutz Brandt, Dr. Zhiming Liu, Craig Rhodine and Tafadzwa Magaya; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: Fabrication of advanced package substrates is a relatively complex process, requiring numerous pretreatment, cleaning, surface preparation, deposition and rinsing steps. In most cases, metalizing a dielectric surface includes some form of activation or “seeding” process, followed by the autocatalytic (or “electroless”) deposition of copper. Reliability depends on sufficient adhesion of this initial copper layer to the dielectric surface. Specifically, this metallization must withstand normal mechanical stresses imposed by the subsequent electrolytic copper deposit, thermal stresses encountered in downstream substrate processing steps (i.e., soldering) and both thermal and mechanical stresses encountered through the normal operation of the final system. This paper reveals a novel approach for treating and preparing the dielectric surface for the subsequent deposition of electroless copper. Data demonstrate improved copper-to-dielectric adhesion resulting from such treatment. Measurable improvements in the overall reliability of the substrate, attributable to use of this adhesion promotion process, are established. (SMTA Pan Pac Symposium, February 2012)

Solder Bumping

“Process Characterization of Wafer Copper Pillar Bump”

Authors: Wei Koh and Barry Lin; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: Fine-pitch copper pillar bumps (CPB) with bump-to-bump pitch less than 90 µm are increasingly being adopted in flip-chip package assemblies. This paper presents a number of interesting and useful findings during the process of fabricating fine-pitch copper pillar bumps on 300mm wafers for use in advanced, fine pitch and high I/O wafer level packages. The copper pillar bump construction is based on the IBM metal post solder chip connection (MPS-C2) design, with a slim post and a Pb- free solder cap (Sn or SnAg) on top. For initial qualification build, the MPS-C2 bumps are built both directly on the pads (bump on pad, BOP) and on pads built on redistributed layers (bump on RDL). Using a daisy-chain test chip, the BOP bumps are located on the peripheral, and the bumps on RDL are located in the center in an area array format. Following fairly standard manufacturing process for electrodeposited wafer bumping, the unit processes include wafer cleaning, micro back-etch, UBM/seed layer metal deposition, photoresist development and patterning, electroplating of the copper and the solder cap, resist stripping, visual inspection and solder reflow. After singulation, test chips are flip-chip-bonded to mating substrates with copper pads for solder joint evaluation. During some unit process operations, such as electrodeposition and photoresist removal, some abnormalities in the CPB formation have been discovered, mainly due to the particular process characteristics applied during the evaluation. This paper presents several of these abnormal phenomena found and discusses process characteristics and causes that led to such problems. (SMTA Pan Pac Symposium, February 2012)


“The Coffin-Manson Formula for Sn3.0Ag0.5Cu Solder Joints”

Authors: Jao-Hwa Kuang, T. P. Hung, C. M. Hsu, A. D. Lin and C. H. Wu; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: The parameters of Coffin-Manson equation for Pb-free Sn3.0Ag0.5Cu solder joints are derived. The thermal-elastic-plastic finite element model of solder joints is employed to simulate the strain amplitude in the corresponding BGA thermal cycle fatigue tests. The temperature-dependent material properties are considered in the simulation to evaluate the residual stress introduced during the soldering process. Based on the Weibull life assumption, the parameters of Coffin-Manson equation are derived from the thermal cycle fatigue results and the simulated plastic shear strain amplitude. To verify the feasibility and reliability of the proposed formula, the results of isothermal low cycle fatigue test were analyzed experimentally and numerically. A good agreement between the experimental and simulated data is observed. (SMTA Pan Pac Symposium, February 2012)

Technology Commercialization

“SMART Commercialization Center for Microsystems – A New Model to Drive Industry Development”

Author: Chris Mather; This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Abstract: The SMART Commercialization Center for Microsystems at Lorain County Community College represents a new approach to public/private partnerships, and may prove to be a model for spurring technology growth in the US.

The SMART model represents a unique partnership opportunity for the EMS industry. Potential EMS customers can work in such a facility to finalize design prior to manufacturing implementation. SMART can recommend specific EMS partners early in the design cycle, allowing for collaboration and greater likelihood of a business relationship. SMART can make companies more productive, more likely to undertake sensor and microsystems projects, and more likely to do so in the US or their home country. The paper discusses the SMART concept, equipment, programs, and industry approach, and reviews early results. (SMTA Pan Pac Symposium, February 2012)

This column provides abstracts from recent industry conferences and company white papers. Our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.

Last Updated on Friday, 02 March 2012 21:30




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