SerDes, Spice and IBIS-AMI Print E-mail
Written by Patrick Carrier   
Friday, 07 January 2011 23:19

Generating the “eye” can take a lifetime. It doesn’t have to.

One guaranteed aspect of technology advancement is greater speed. But as speeds increase, PCB trace routing affects bus performance, mandating signal integrity analysis as part of the board design.

Another more recent example of truly understanding margins is slew-rate derating when analyzing DDR2 and DDR3 memory designs. Slew-rate derating basically creates a more accurate picture of when an input gate is charging up and switching, versus just using a single voltage threshold for timing information. That level of detail is necessary when the bus operates on margins measured in picoseconds, and the same is true of serializer/deserializer (SerDes) busses, such as PCI Express and SATA, where bit error rates (BER) need to be measured in terms of trillions of bits.

Validating a SerDes bus to a bit error rate of 10-12 requires detailed analysis with appropriate models. Validation is typically performed using an eye diagram – a series of 1s and 0s overlaid on top of one another to give a single picture, or “eye,” representing the timing, signal quality and noise on a channel (Figure 1). The eye diagram is typically measured against an eye mask (shown in blue); violations represent a failure. Since an eye diagram is created using a specific number of bits, however, more data are needed to create a comprehensive characterization of the channel performance.



Accurate channel modeling. No characterization can be obtained without an accurate model of the entire channel (Figure 2). The traces of the PCB are the most important aspect of a bus interconnect. Traces can be modeled using a field solver, and must include accurate models of loss, including all frequency-dependent losses. The losses in the traces are typically the main detractor from performance margins on the bus.



In addition to traces, vias, chip packages and connectors must also be modeled. These are generally modeled as scattering parameters, or S-parameters, created from either a 3D electromagnetic field solver or measurement. S-parameters are frequency-domain models used to represent passive devices, and are one of the most popular model types used in SerDes analysis. But since S-parameters are frequency-domain models, care must be taken by the simulator to generate accurate time-domain results.

Many simulators use convolution to simulate S-parameters in the time domain. Convolution can be slow, and accuracy suffers due to repeated truncation of the convolution integral results. In fact, problems caused by repeated convolution can also appear in other aspects of simulation. Using a complex pole-fitting method, reducing the S-parameter to a set of poles and zeros, can be used directly in simulation, producing fast and accurate results.

Driver and receiver modeling. Driver and receiver models must be added to the interconnect model. Due to the speed and complexity of SerDes models, typical IBIS models cannot be used. Most often used is Spice, which permits buffer modeling at the transistor geometry level, and all the complex pre-emphasis and equalization circuitry found in SerDes buffers. However, Spice can take several hours to generate an eye diagram for a couple hundred bits. Simulating the trillions of bits necessary to validate the SerDes BER would take hundreds of thousands of years, so new modeling or simulation methods are necessary.

The IBIS committee sought to solve this problem in 2004 with the [External Model] and [External Circuit] keywords, which allowed mapping an IBIS model to a VHDL-AMS or Verilog-AMS model, in addition to Spice. The *-AMS modeling languages permit modeling I/Os using higher-level behavioral models, providing the flexibility of Spice with the speed of IBIS models. Recently, the committee added support for IBIS-AMI models, executable models using a new kind of analysis: channel analysis.

Channel analysis, or fast eye-diagram creation, uses impulse and/or step responses of a SerDes channel to create eye diagrams in a fraction of the time of traditional transient simulation. However, the channel must be linear (determined by driver behavior in the operating region) and time invariant for this analysis to be accurate. This analysis can be performed with any kind of model: Spice, VHDL-AMS or Verilog-AMS, or IBIS-AMI. IBIS-AMI models actually require this kind of analysis to function.

Convolution is most often used for converting pulse response data to transient eye-diagram data. But, just as with S-parameter simulation, repeated use of the convolution integral leads to errors in results caused by local truncation error. Because the high number of convolution iterations can be so high, performance is increased by truncating the results in each step, which can accumulate to large errors over time. This problem can be eliminated using an internal state variable method that produces accurate results in a short time.

Whether using an IBIS-AMI model, or a Spice or AMS model, results are obtained much faster than traditional bit-by-bit simulation. Thus, prediction of BER of 10-12 and 10-15 are possible. Accurately predicting such bit error rates requires a transient simulation algorithm, usually began by using a pseudo-random bit stream of about 107 bits. But such methods often lead to inaccuracies predicting bit error rates of 10-12. Some tools use a worst-case bit sequence as the starting point for their predication algorithms, which permits inclusion of deterministic jitter, duty-cycle distortion and crosstalk for the final results, generating an accurate BER prediction.

The sample results (Figure 3) show different ways of looking at the same data. Statistical contours show the eye opening in terms of BER, similar to the bathtub curves that indicate eye width variance with BER. Eye density plots, shown in both two and three dimensions, indicate the worst-case eye diagram for the channel, including the bit recurrence in different locations of the eye (represented by different colors and the z-axis of the 3D plot).

All these results, based on accurate simulation of the channel, are generated orders of magnitude faster than it would take traditional bit-by-bit transient simulation using Spice models. Through the combination of new modeling techniques, as well as innovative simulation techniques that appropriately handle different types of channel characterization and frequency-dependent models, appropriate characterization of SerDes channels are now possible.

Patrick Carrier is a technical marketing engineer for high-speed PCB analysis tools at Mentor Graphics (mentor.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Last Updated on Saturday, 08 January 2011 00:36
 

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