'FPGA for Test' Trend Highlighted in NI Report
Written by Mike Buetow   
Friday, 17 February 2012 14:36

AUSTIN, TX -- National Instruments has released its annual look at test and measurement technology and methodology trends.

Add a comment
Read more...
 
Isola Ramping Production on New High-Speed Laminate
Written by Mike Buetow   
Friday, 17 February 2012 13:57

CHANDLER, AZ -- Isola Group has completed of the beta testing and internal qualification for I-Speed, the company's lead-free compatible, low-loss, high-speed digital laminate.

Add a comment
Read more...
 

Search

Search

Login

CB Login

Language

Language

English French German Italian Portuguese Russian Spanish
 

Features

Specifying QFN Stencils and Solder Layers
When it comes to paste coverage, less is more. I write a lot about things that go wrong with various layouts. Hopefully by doing that, I can help some readers avoid common pitfalls. But I should probably write about more good things to balance them out.Here’s a decent example. Figure 1 shows a good way to specify the solder paste layer for QFN parts. Notice that the center thermal area is segmented to give about 50% paste coverage. This...
Printed Circuit Design & Fab Magazine on Facebook